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Synplify user guide Synplicity FPGA Synthesis Synplify Synplify Pro Synplify Premier and Synplify Premier with Design Planner Synplicity Inc West California Avenue Sunnyvale CA U S - direct U S - fax www synplicity com User Guide December CPreface Preface

Synplicity FPGA Synthesis Synplify Synplify Pro Synplify Premier and Synplify Premier with Design Planner Synplicity Inc West California Avenue Sunnyvale CA U S - direct U S - fax www synplicity com User Guide December CPreface Preface Disclaimer of Warranty Synplicity Inc makes no representations or warranties either expressed or implied by or with respect to anything in this manual and shall not be liable for any implied warranties of merchantability or ?tness for a particular purpose of for any indirect special or consequential damages Copyright Notice Copyright ? - Synplicity Inc All Rights Reserved Synplicity software products contain certain con ?dential information of Synplicity Inc Use of this copyright notice is precautionary and does not imply publication or disclosure No part of this publication may be reproduced transmitted transcribed stored in a retrieval system or translated into any language in any form by any means without the prior written permission of Synplicity Inc While every precaution has been taken in the preparation of this book Synplicity Inc assumes no responsibility for errors or omissions This publication and the features described herein are subject to change without notice Trademarks Synplicity the Synplicity ??S ? logo Amplify Amplify ASIC Amplify FPGA Behavior Extracting Synthesis Technology Certify Embedded Synthesis Fortify HDL Analyst PowerTime RealPower SCOPE Simply Better Results Simply Better Synthesis Syndicated Synplify Synplify ASIC Synplify Lite Synplify Pro and Synthesis Constraint Optimization Environment are registered trademarks of Synplicity Inc BEST DST Direct Synthesis Technology Identify IICE MultiPoint Partition-Driven Synthesis Physical Analyst Physical Optimizer PowerPlanner PowerRoute Synplify IP TOPS and Total Optimization Physical Synthesis are trademarks of Synplicity Inc Verilog is a registered trademark of Cadence Design Systems Inc IBM and PC are registered trademarks of International Business Machines Corpo- ration Microsoft is a registered trademark of Microsoft Corporation Sun SPARC Solaris and SunOSLaOre trademarks of Sun Microsystems Inc UNIX is a registered trademark of X Open Corporation All other product names mentioned herein are the trademarks or registered trademarks of their respective owners ii Fpga User Guide December CPreface Restricted Rights Legend Government Users Use reproduction release modi ?cation or disclosure of this commercial computer software or of any related documentation of any kind is restricted in accordance with FAR and DFARS and further restricted by the Synplicity Software License Agreement Synplicity Inc West California Avenue Sunnyvale CA U S A Printed in the U S A December Fpga User Guide December iii CPreface Synplicity Software License Agreement Important READ CAREFULLY BEFORE PROCEEDING BY INDICATING YOUR ACCEPTANCE OF THE TERMS OF THIS AGREEMENT YOU ??LICENSEE ? ARE REPRESENTING THAT YOU HAVE THE RIGHT AND AUTHORITY TO LEGALLY BIND YOURSELF OR YOUR COMPANY AS APPLICABLE AND CONSENTING TO BE LEGALLY BOUND BY ALL OF THE TERMS OF THIS AGREEMENT IF YOU DO NOT AGREE TO ALL THESE TERMS DO NOT INSTALL OR USE THE SOFTWARE AND RETURN THE SOFTWARE TO THE LOCATION OF PURCHASE FOR A REFUND This is a legal agreement governing use of the software program provided by Synplicity Inc