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User guide 69 Certify Partition Driven Synthesis User Guide March http solvnet synopsys com CDisclaimer of Warranty Synopsys Inc makes no representations or warranties either expressed or implied by or with respect to anything in this manual and shall not

Certify Partition Driven Synthesis User Guide March http solvnet synopsys com CDisclaimer of Warranty Synopsys Inc makes no representations or warranties either expressed or implied by or with respect to anything in this manual and shall not be liable for any implied warranties of merchantability or ?tness for a particular purpose of for any indirect special or consequential damages Copyright Notice Copyright ? Synopsys Inc All Rights Reserved Synopsys software products contain certain con ?dential information of Synopsys Inc Use of this copyright notice is precautionary and does not imply publication or disclosure No part of this publication may be reproduced transmitted transcribed stored in a retrieval system or translated into any language in any form by any means without the prior written permission of Synopsys Inc While every precaution has been taken in the preparation of this book Synopsys Inc assumes no responsibility for errors or omissions This publication and the features described herein are subject to change without notice Trademarks Registered Trademarks Synopsys AMPS Astro Behavior Extracting Synthesis Technology Cadabra CATS Certify CHIPit CoMET Design Compiler DesignWare Formality Galaxy Custom Designer HAPS HapsTrak HDL Analyst HSIM HSPICE Identify Leda MAST METeor ModelTools NanoSim OpenVera PathMill Physical Compiler PrimeTime SCOPE Simply Better Results SiVL SNUG SolvNet Syndicated Synplicity the Synplicity logo Synplify Synplify Pro Synthesis Constraints Optimization Environment TetraMAX UMRBus VCS Vera and YIELDirector are registered trademarks of Synopsys Inc Trademarks AFGen Apollo Astro-Rail AsLtOro-Xtalk Aurora AvanWaves BEST Columbia Columbia- CE Cosmos CosmosLE CosmosScope CRITIC DC Expert DC Professional DC Ultra Design Analyzer Design Vision DesignerHDL DesignPower Direct Silicon Access Discovery Eclypse Encore EPIC Certify User Guide March CGalaxy HANEX HAPS HapsTrak HDL Compiler Hercules Hierarchical Optimization Technology High-performance ASIC Prototyping System HSIM HSIMplus i-Virtual Stepper IICE in-Sync iN-Tandem Jupiter Jupiter-DP JupiterXT JupiterXT-ASIC Liberty Libra-Passport Library Compiler Magellan Mars Mars-Rail Mars-Xtalk Milkyway ModelSource Module Compiler MultiPoint Physical Analyst Planet Planet-PL Polaris Power Compiler Raphael Saturn Scirocco Scirocco-i Star-RCXT Star-SimXT System Compiler System Designer Taurus TotalRecall TSUPREM- VCS Express VCSi VHDL Compiler VirSim and VMC are trademarks of Synopsys Inc Service Marks SM MAP-in SVP Café and TAP-in are service marks of Synopsys Inc SystemC is a trademark of the Open SystemC Initiative and is used under license ARM and AMBA are registered trademarks of ARM Limited Saber is a registered trademark of SabreMark Limited Partnership and is used under license All other product or company names may be trademarks of their respective owners Restricted Rights Legend Government Users Use reproduction release modi ?cation or disclosure of this commercial computer software or of any related documentation of any kind is restricted in accordance with FAR and DFARS and further restricted by the Synopsys Software License and Maintenance Agreement Synopsys Inc Synplicity Business Group East Middle ?eld Road Mountain View CA U S A March Certify User Guide March CLO Certify User Guide March CContents Chapter ASIC Prototyping Using FPGAs What is Prototyping What is the Certify Prototyping Tool About This Manual Introduction The Synopsys FPGA Product Family The FPGA Synthesis