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Layout Design Entry, Verification, and Automation User Guide Page 2 last modifi

Layout Design Entry, Verification, and Automation User Guide Page 2 last modified 6/27/05 Table Of Contents Layout Design Entry, Verification, and Automation User Guide 1 Chapter 1 Overview of the Layout Design Flow 4 Overview of the Design Flow 4 Generate Layout 5 Check Nets and Pins 7 DRC 7 LVS 8 Netlist and Simulate 8 Chapter 2 Virtuoso 10 Suggested Settings 10 The Device Library 11 display.drf 12 SDL 12 Pins/Labels from Schematic 13 Iterated Pin Creation 16 Iterated Selection 18 Place Bus 22 Pin Check and Fix 24 Leadframe Tool 27 Chapter 3 Design Entry Layers 28 Opus 4.4 Layer List 28 Pins 35 Net Labels 36 Resistor 37 Fuse 37 Page 3 last modified 6/27/05 Short 38 Options 38 Mask Layers 39 BJT Devices 41 Special Areaid Layers 42 Unusual Transistors 43 Boundary Layers 44 Chapter 4 Created Layers 45 Overview 45 Modifying Created Layers Directly 46 Created Layers Algorithms 47 Waffling procedure 51 Chapter 5 VCR User’s Guide 54 Introduction 54 VCR Design Flow 59 Prepare design for Translation 60 Translate from Virtuoso to VCR 62 VCR data structure 66 VCR environment 69 Placement Mode 73 Interactive Routing Mode 78 Set Rules For Auto-Route 88 Advanced Rule Setting 95 Auto-router 109 Using VCR reports to check routing results 117 Introduction to Cadence Chip Assembly Router 122 Save Result and Translate back to Virtuoso 127 Further Reading 130 Chapter 6 Calibre 131 Page 4 last modified 6/27/05 Overview of the Layout Design Flow Chapter 1: Overview of the Layout Design Flow This chapter provides an overview of the layout entry design flow. This chapter does not provide details on how tools work, only a high level ordering of tasks and a description of each task. At any point, if a problem is detected, it means going all the way back to the generate layout step and re- quires running every subsequent step after any change to the layout. Each of these chapters has a more detailed breakdown in a subsequent chapter. Section 1: Overview of the Design Flow Layout design is the process of creating an electrically equivalent, physical, transistor level repre- sentation of a circuit. Generally, a schematic must exist for each layout and vice versa. In some cases, however, a layout may have more or less hierarchy than its corresponding schematic. Fol- lowing is the flowchart for the layout design flow. Page 5 last modified 6/27/05 Overview of the Layout Design Flow Figure 1.1.1: Layout Design Flowchart Section 2: Generate Layout In its simplest form, layout creation involves editing polygons which form devices and routing. Generate Layout DRC Check Nets & Pins Created Layer DRCs LVS Netlist Layout for Hspice Simulate Bad Extremely Bad Go Back To Circuit Design Move On to the Parent Cell Bad Page 6 last modified 6/27/05 Overview of the Layout Design Flow This is called full custom layout, where every polygon is hand edited to minimize size and maxi- mize speed. There are a number of tools which speed layout creation by using information in the schematic and by using layout pcells. The Cypress design flow supports a number of layout methodologies rang- ing from full custom to standard cell place and route. Table 1.2.1: Layout Automation Tools Tool Name Description Pins/Labels from Sch... Speeds pin placement in the layout. Pin Check and Fix Allows modifying pin shapes, ﬁxing nets, deletion of unused pins Place Bus Interactively draws a bus on grid. Iterated Pin Creation Speeds pitch matched pin placement. Iterated Selection Allows selection of regularly placed objects in a layout Schematic Driven Layout (SDL) Speeds creation of layout by placing layout building blocks in the layout. The user must arrange these blocks manually and then route them together. ICcraftsman Used to route together user blocks. Works well with SDL and can be used for top level chip routing. Can be used in an interactive or automatic mode. Silicon Ensemble Automatically generates a layout from a schematic using ﬁxed standard cells with a place and route algorithm. Handles much larger circuits than LAS but with reduced efﬁciency. This is nor- mally used in a logic engine design ﬂow. IP Library Borrowing The fastest way to enter a layout is to borrow it from someone else. Page 7 last modified 6/27/05 Overview of the Layout Design Flow Section 3: Check Nets and Pins In the Layout Editor, the program Pin Check and Fix is available from the Cypress pulldown menu. This program should be run on all full custom layout blocks to verify that the pins are formed well. Also, from the symbol editor, there is a cross view check utility which will verify that the terminals of various views match. By default, the layout is not included in this list. It is often useful to add the layout to this list where the terminals in the layout are important. Section 4: DRC Each technology has a TDR spec (Technology Design Rules). This spec is verified through a De- sign Rule Check rules file. It is recommended to run DRC after each layout cellview is created. This allows a designer to deal with errors early in the design. It is required to run DRC on the full chip layout before tapeout. Errors must be either fixed or signed off. Created Layers DRC must also be run for the full chip. This is largely the same as DRC, but it in- volves generating created layers first and then verifying the created layers for errors. This is not normally run for each cellview, but is required to be run at block level before the block is consid- ered clean. Page 8 last modified 6/27/05 Overview of the Layout Design Flow Section 5: LVS LVS is a check which verifies the Layout Versus the Schematic. It extracts devices and nets in the layout and compares them to the schematic to ensure that the same number of devices exist, the same number of nets exist, and the connectivity of the devices and nets are identical, and the de- vices themselves are identical. This check is required for the top level layout and schematic of a chip before tapeout. After verilog netlisting and clean LVS, you can run fuseGen to dump a fuse table. Then use fuseapp to perform ad-hoc queries and to program fuses specified by location or name or description match- ing. Section 6: Netlist and Simulate The backend simulation flow is undergoing a lot of work. There are two basic models currently supported. Either way, Vampire is used to generate an Hspice netlist of a layout. Ì Extract key leaf cells for a hand built critical path Hspice simulation. The netlist is used as part of a simulation schematic which models a specific critical path with great accuracy. Hspice cannot handle a full chip simulation, but a simulation schematic can be built which includes extracted hspice netlists for critical path simulations. Page 9 last modified 6/27/05 Overview of the Layout Design Flow Ì Extract the full chip for a Timemill simulation. In this methodology, the full chip is verified for functionality and speed, but Timemill is not as ac- curate as Hspice. In areas where Timemill says the chip is very close to its spec, Hspice should be used to obtain a more accurate measurement to make sure the chip is within spec. Page 10 last modified 6/27/05 Virtuoso Chapter 2: Virtuoso Virtuoso is the name of the Cadence Layout Editor. This editor is documented in Cadence open- book. This chapter provides: • provides a quick overview of differences between Opus 4.3.4 and Opus 4.4 • highlights Cypress customizations to Virtuoso Section 1: Suggested Settings There are a few settings which many users will want to put in their .cdsenv file. By default, pin names in a layout are hidden. This tells opus to show them. layout displayPinNames boolean t These two lines set the snap spacing in the layout. This can vary from one technology to another. If geometries are placed off grid, DRC will generate errors. layout ySnapSpacing float 0.025 layout xSnapSpacing float 0.025 In order to select the edge of a geometry or a set of geometries to stretch them, this option must be set. layout partialSelect boolean t This option enables the infix user entry mode. With this mode of operation, whenever possible, Ca- dence will use the mouse location when a command is executed as the first entry point. ui infix boolean t Page 11 last modified 6/27/05 Virtuoso Section 2: The Device Library Creation of the device library and a detailed description of how technology information is managed is found in Chapter 11 of the Design Management User Guide. The device library is used by layout automation tools to create a symbolic layout. The device li- brary is also used by designers directly to speed the creation of often used devices. The device library is broken into the following categories: Capacitors Contains the poly capacitor devices. Contacts Contains various contact structures. LAS Contains pcells which LAS uses. uploads/Ingenierie_Lourd/ layout-guide 1 .pdf