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Reference guide 2 TMS C x C x DSP CPU and Instruction Set Reference Guide Literature Number SPRU J July SPRU J ?? July Copyright ? Texas Instruments Incorporated Contents Preface Introduction TMS DSP Family Overview TMS C DSP Family Overview TMS C x DSP F

TMS C x C x DSP CPU and Instruction Set Reference Guide Literature Number SPRU J July SPRU J ?? July Copyright ? Texas Instruments Incorporated Contents Preface Introduction TMS DSP Family Overview TMS C DSP Family Overview TMS C x DSP Features and Options TMS C x C x DSP Architecture Central Processing Unit CPU Internal Memory Memory and Peripheral Options CPU Data Paths and Control Introduction General-Purpose Register Files Functional Units Register File Cross Paths Memory Load and Store Paths Data Address Paths Galois Field Special Timing Considerations Control Register File Register Addresses for Accessing the Control Registers Pipeline Timing of Control Register Accesses Addressing Mode Register AMR Control Status Register CSR Galois Field Polynomial Generator Function Register GFPGFR Interrupt Clear Register ICR Interrupt Enable Register IER Interrupt Flag Register IFR Interrupt Return Pointer Register IRP Interrupt Set Register ISR Interrupt Service Table Pointer Register ISTP Nonmaskable Interrupt NMI Return Pointer Register NRP E Phase Program Counter PCE Control Register File Extensions Debug Interrupt Enable Register DIER DSP Core Number Register DNUM Exception Clear Register ECR Exception Flag Register EFR GMPY Polynomial ??A Side Register GPLYA GMPY Polynomial ??B Side Register GPLYB Internal Exception Report Register IERR SPLOOP Inner Loop Count Register ILC Interrupt Task State Register ITSR NMI Exception Task State Register NTSR Restricted Entry Point Register REP SPLOOP Reload Inner Loop Count Register RILC SPRU J ?? July Contents Copyright ? Texas Instruments Incorporated www ti com Saturation Status Register SSR Time Stamp Counter Registers TSCL and TSCH Task State Register TSR Instruction Set Instruction Operation and Execution Notations Instruction Syntax and Opcode Notations -Bit Opcode Maps -Bit Opcode Maps Delay Slots Parallel Operations Example Parallel Code Branching Into the Middle of an Execute Packet Conditional Operations SPMASKed Operations Resource Constraints Constraints on Instructions Using the Same Functional Unit Constraints on the Same Functional Unit Writing in the Same Instruction Cycle Constraints on Cross Paths X and X Cross Path Stalls Constraints on Loads and Stores Constraints on Long -Bit Data Constraints on Register Reads Constraints on Register Writes Constraints on AMR Writes Constraints on Multicycle NOPs Constraints on Unitless Instructions Addressing Modes Linear Addressing Mode Circular Addressing Mode Syntax for Load Store Address Generation Compact Instructions on the C x CPU Compact Instruction Overview Header Word Format Processing of Fetch Packets Execute Packet Restrictions Available Compact Instructions Instruction Compatibility Instruction Descriptions Pipeline Pipeline Operation Overview Fetch Decode Execute Pipeline Operation Summary Pipeline Execution of Instruction Types Single-Cycle Instructions Two-Cycle Instructions and M Unit Nonmultiply Operations Store Instructions Extended Multiply Instructions Load Instructions Branch Instructions Performance Considerations Pipeline Operation With Multiple Execute Packets in a Fetch Packet Contents SPRU J ?? July Copyright ? Texas Instruments Incorporated www ti com Multicycle NOPs Memory Considerations C x DSP Differences Interrupts Overview Types of Interrupts and Signals Used Interrupt Service Table IST Summary of Interrupt Control Registers Globally Enabling and Disabling Interrupts Individual Interrupt Control Enabling and Disabling Interrupts Status of Interrupts Setting and Clearing Interrupts Returning From