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May 2013 Altera Corporation UG-MFNALT_FIFO-8.2 User Guide © 2013 Altera Corpora

May 2013 Altera Corporation UG-MFNALT_FIFO-8.2 User Guide © 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 101 Innovation Drive San Jose, CA 95134 www.altera.com Feedback Subscribe ISO 9001:2008 Registered SCFIFO and DCFIFO Megafunctions Altera provides FIFO functions through the parameterizable single-clock FIFO (SCFIFO) and dual-clock FIFO (DCFIFO) megafunctions. The FIFO functions are mostly applied in data buffering applications that comply with the first-in-first-out data flow in synchronous or asynchronous clock domains. The specific names of the megafunctions are as follows: ■ SCFIFO: single-clock FIFO ■ DCFIFO: dual-clock FIFO (supports same port widths for input and output data) ■ DCFIFO_MIXED_WIDTHS: dual-clock FIFO (supports different port widths for input and output data) 1 In this user guide, the term “DCFIFO” refers to both the DCFIFO and DCFIFO_MIXED_WIDTHS megafunctions, unless specified. This user guide contains the following sections: ■ “Configuration Methods” on page 2 ■ “Specifications” on page 2 ■ “Parameter Specifications” on page 10 ■ “Functional Timing Requirements” on page 13 ■ “Output Status Flags and Latency” on page 15 ■ “Metastability Protection and Related Options” on page 17 ■ “Synchronous Clear and Asynchronous Clear Effect” on page 19 ■ “Different Input and Output Width” on page 21 ■ “Constraint Settings” on page 22 ■ “Coding Example for Manual Instantiation” on page 23 ■ “Design Example” on page 24 1 Before you configure and build the FIFO megafunction, refer to “Specifications” on page 2 and “Parameter Specifications” on page 10. The description about input ports, output ports, and parameters is important especially if you decide to manually instantiate the megafunctions. Page 2 Configuration Methods SCFIFO and DCFIFO Megafunctions May 2013 Altera Corporation Configuration Methods You can configure and build the FIFO megafunctions with the following methods: ■ Using the FIFO parameter editor launched from the MegaWizard™ Plug-In Manager in the Quartus® II software. Altera recommends using this method to build your FIFO megafunctions. It is an efficient way to configure and build the FIFO megafunctions. The FIFO parameter editor provides options that you can easily use to configure the FIFO megafunctions. f For general information about the Quartus II MegaWizard Plug-In Manager, refer to the Megafunction Overview User Guide. ■ Manually instantiating the FIFO megafunctions. Use this method only if you are an expert user. This method requires that you know the detailed specifications of the megafunctions. You must ensure that the input and output ports used, and the parameter values assigned are valid for the FIFO megafunction you instantiate for your target device. For coding examples about how to manually instantiate the FIFO megafunctions, you can refer to “Coding Example for Manual Instantiation” on page 23. Specifications This section describes the prototypes, component declarations, ports, and parameters of the SCFIFO and DCFIFO megafunctions. These ports and parameters are available to customize the SCFIFO and DCFIFO megafunctions according to your application. Verilog HDL Prototype You can locate the following Verilog HDL prototypes in the Verilog Design File (.v) altera_mf.v in the <Quartus II installation directory>\eda\synthesis directory. SCFIFO module scfifo #( parameter add_ram_output_register = "OFF", parameter allow_rwcycle_when_full = "OFF", parameter almost_empty_value = 0, parameter almost_full_value = 0, parameter intended_device_family = "unused", parameter lpm_numwords = 1, parameter lpm_showahead = "OFF", parameter lpm_width = 1, parameter lpm_widthu = 1, parameter overflow_checking = "ON", parameter underflow_checking = "ON", parameter use_eab = "ON", parameter lpm_type = "scfifo", parameter lpm_hint = "unused") ( input wire aclr, output wire almost_empty, output wire almost_full, Specifications Page 3 SCFIFO and DCFIFO Megafunctions May 2013 Altera Corporation input wire clock, input wire [lpm_width-1:0] data, output wire empty, output wire full, output wire [lpm_width-1:0] q, input wire rdreq, input wire sclr, output wire [lpm_widthu-1:0] usedw, input wire wrreq)/* synthesis syn_black_box=1 */; endmodule DCFIFO module dcfifo_mixed_widths #( parameter add_ram_output_register = "OFF", parameter add_usedw_msb_bit = "OFF", parameter clocks_are_synchronized = "FALSE", parameter delay_rdusedw = 1, parameter delay_wrusedw = 1, parameter intended_device_family = "unused", parameter lpm_numwords = 1, parameter lpm_showahead = "OFF", parameter lpm_width = 1, parameter lpm_width_r = 0, parameter lpm_widthu = 1, parameter lpm_widthu_r = 1, parameter overflow_checking = "ON", parameter rdsync_delaypipe = 0, parameter underflow_checking = "ON", parameter use_eab = "ON", parameter write_aclr_synch = "OFF", parameter read_aclr_synch = "OFF", parameter wrsync_delaypipe = 0, parameter lpm_type = "dcfifo_mixed_widths", parameter lpm_hint = "unused") ( input wire aclr, input wire [lpm_width-1:0] data, output wire [lpm_width_r-1:0] q, input wire rdclk, output wire rdempty, output wire rdfull, input wire rdreq, output wire [lpm_widthu_r-1:0] rdusedw, input wire wrclk, output wire wrempty, output wire wrfull, input wire wrreq, output wire [lpm_widthu-1:0] wrusedw)/* synthesis syn_black_box=1 */; endmodule //dcfifo_mixed_widths Page 4 Specifications SCFIFO and DCFIFO Megafunctions May 2013 Altera Corporation VHDL Component Declaration You can locate the following VHDL component declarations in the VHDL Design File (.vhd) altera_mf.vhd in the <Quartus II installation directory>\libraries\vhdl\altera_mf directory. SCFIFO component scfifo generic ( add_ram_output_register: string := "OFF"; allow_rwcycle_when_full: string := "OFF"; almost_empty_value: natural := 0; almost_full_value: natural := 0; intended_device_family: string := "unused"; lpm_numwords: natural; lpm_showahead: string := "OFF"; lpm_width: natural; lpm_widthu: natural := 1; overflow_checking: string := "ON"; underflow_checking: string := "ON"; use_eab: string := "ON"; lpm_hint: string := "UNUSED"; lpm_type: string := "scfifo" ); port( aclr: in std_logic := '0'; almost_empty: out std_logic; almost_full: out std_logic; clock: in std_logic; data: in std_logic_vector(lpm_width-1 downto 0); empty: out std_logic; full: out std_logic; q : out std_logic_vector(lpm_width-1 downto 0); rdreq: in std_logic; sclr: in std_logic := '0'; usedw: out std_logic_vector(lpm_widthu-1 downto 0); wrreq: in std_logic ); end component; DCFIFO component dcfifo_mixed_widths generic ( add_ram_output_register: string := "OFF"; add_usedw_msb_bit: string := "OFF"; clocks_are_synchronized: string := "FALSE"; delay_rdusedw: natural := 1; delay_wrusedw: natural := 1; intended_device_family: string := "unused"; lpm_numwords: natural; lpm_showahead: string := "OFF"; lpm_width: natural; lpm_width_r: natural := 0; lpm_widthu: natural := 1; lpm_widthu_r: natural := 1; Specifications Page 5 SCFIFO and DCFIFO Megafunctions May 2013 Altera Corporation overflow_checking: string := "ON"; rdsync_delaypipe: natural := 0; underflow_checking:string := "ON"; use_eab: string := "ON"; write_aclr_synch: string := "OFF"; wrsync_delaypipe: natural := 0; read_aclr_synch: string := "OFF"; lpm_hint: string := "UNUSED"; lpm_type: string := "dcfifo_mixed_widths" ); port( aclr: in std_logic := '0'; data: in std_logic_vector(lpm_width-1 downto 0); q : out std_logic_vector(lpm_width_r-1 downto 0); rdclk: in std_logic; rdempty: out std_logic; rdfull: out std_logic; rdreq: in std_logic; rdusedw: out std_logic_vector(lpm_widthu_r-1 downto 0); wrclk: in std_logic; wrempty: out std_logic; wrfull: out std_logic; wrreq: in std_logic; wrusedw: out std_logic_vector(lpm_widthu-1 downto 0) ); end component; VHDL LIBRARY-USE Declaration The VHDL LIBRARY-USE declaration is not required if you use the VHDL component declaration. LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; Page 6 Specifications SCFIFO and DCFIFO Megafunctions May 2013 Altera Corporation Ports Specifications This section provides diagrams of the SCFIFO and DCFIFO blocks to help in visualizing their input and output ports. This section also describes each port in detail to help in understanding their usages, functionality, or any restrictions. For better illustrations, some descriptions might refer you to a specific section in this user guide. Figure 1 shows the input and output ports of the SCFIFO and DCFIFO megafunctions. For the SCFIFO block, the read and write signals are synchronized to the same clock; for the DCFIFO block, the read and write signals are synchronized to the rdclk and wrclk clocks respectively. The prefixes wr and rd represent the signals that are synchronized by the wrclk and rdclk clocks respectively. Figure 1. Input and Output Ports SCFIFO data[7..0] wrreq rdreq sclr aclr clock almost_full almost_empty usedw[7..0] empty full q[7..0] DCFIFO data[7..0] wrreq rdreq wrempty aclr rdempty rdusedw[8..0] wrclk wrusedw[8..0] q[7..0] rdfull wrfull rdclk Specifications Page 7 SCFIFO and DCFIFO Megafunctions May 2013 Altera Corporation Table 1 describes the ports of the megafunctions. 1 The term “series” refers to all the device families of a particular device. For example, “Stratix series” refers to the Stratix®, Stratix GX, Stratix II, Stratix II GX, Stratix III, and new devices, unless specified otherwise. Table 1. Input and Output Ports Description (Part 1 of 3) Port Type Required Description clock (1) Input Yes Positive-edge-triggered clock. wrclk (2) Input Yes Positive-edge-triggered clock. Use to synchronize the following ports: ■ data ■ wrreq ■ wrfull ■ wrempty ■ wrusedw rdclk (2) Input Yes Positive-edge-triggered clock. Use to synchronize the following ports: ■ q ■ rdreq ■ rdfull ■ rdempty ■ rdusedw data (3) Input Yes Holds the data to be written in the FIFO uploads/s1/ fifo-user-guide-pdf.pdf