BluespecTM SystemVerilog Reference Guide Revision: 16 June 2010 Copyright c ⃝20

BluespecTM SystemVerilog Reference Guide Revision: 16 June 2010 Copyright c ⃝2000 – 2010 Bluespec, Inc. All rights reserved 1 Reference Guide Bluespec SystemVerilog Trademarks and copyrights Verilog is a trademark of IEEE (the Institute of Electrical and Electronics Engineers). The Verilog standard is copyrighted, owned and maintained by IEEE. VHDL is a trademark of IEEE (the Institute of Electrical and Electronics Engineers). The VHDL standard is copyrighted, owned and maintained by IEEE. SystemVerilog is a trademark of Accellera, Inc. The SystemVerilog standard is owned and maintained by Accellera. Bluespec is a trademark of Bluespec, Inc. AzureIP is a trademark of Bluespec, Inc. 2 Bluespec SystemVerilog Reference Guide Contents Table of Contents 3 1 Introduction 13 1.1 Meta notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Lexical elements 13 2.1 Whitespace and comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 Identifiers and keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 Integer literals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.1 Type conversion of integer literals . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4 Real literals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4.1 Type conversion of real literals . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5 String literals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6 Don’t-care values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7 Compiler directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7.1 File inclusion: ‘include and ‘line . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7.2 Macro definition and substitution: ‘define and related directives . . . . . . . 18 2.7.3 Conditional compilation: ‘ifdef and related directives . . . . . . . . . . . . . . 19 3 Packages and the outermost structure of a BSV design 20 3.1 Scopes, name clashes and qualified identifiers . . . . . . . . . . . . . . . . . . . . . . 21 3.2 The Standard Prelude package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 AzureIPTM Foundation Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 Types 22 4.1 Polymorphism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 Provisos (brief intro) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2.1 The pseudo-function valueof (or valueOf) . . . . . . . . . . . . . . . . . . . . 26 4.3 A brief introduction to deriving clauses . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 Modules and interfaces, and their instances 27 5.1 Explicit state via module instantiation, not variables . . . . . . . . . . . . . . . . . . 27 5.2 Interface declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.1 Subinterfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3 Module definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.4 Module and interface instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4.1 Short form instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3 Reference Guide Bluespec SystemVerilog 5.4.2 Long form instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.5 Interface definition (definition of methods) . . . . . . . . . . . . . . . . . . . . . . . . 35 5.5.1 Shorthands for Action and ActionValue method definitions . . . . . . . . . . 36 5.5.2 Definition of subinterfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.5.3 Definition of methods and subinterfaces by assignment . . . . . . . . . . . . . 38 5.6 Rules in module definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.7 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.8 Synthesizing Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.8.1 Type Polymorphism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.8.2 Module Interfaces and Arguments . . . . . . . . . . . . . . . . . . . . . . . . 43 6 Static and dynamic semantics 44 6.1 Static semantics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.1 Type checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.2 Proviso checking and bit-width constraints uploads/s3/ reference-guide 3 .pdf

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