Remerciez-le!

Remerciez @Admin pour avoir partagé cet document gratuitement, de la manière la plus simple, en partageant sur les réseaux sociaux.

FPGA PROTOTYPING BY VHDL EXAMPLES Xilinx SpartanTm-3 Version Pong P. Chu Clevel

FPGA PROTOTYPING BY VHDL EXAMPLES Xilinx SpartanTm-3 Version Pong P. Chu Cleveland State University 47 INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION CONTENTS Preface Acknowledgments PART I BASIC DIGITAL CIRCUITS xix xxv 1 Gate-level combinational circuit 1 1.1 Introduction 1 1.2 General description 2 1.2.1 Basic lexical rules 2 1.2.2 Library and package 3 1.2.3 Entity declaration 3 1.2.4 Data type and operators 3 1.2.5 Architecture body 4 1.2.6 Code of a 2-bit comparator 5 1.3 Structural description 6 1.4 Testbench 8 1.5 Bibliographie notes 9 1.6 Suggested experiments 10 1.6.1 Code for gate-level greater-than circuit 10 1.6.2 Code for gate-level binary decoder 10 2 Overview of FPGA and EDA software 11 vii Viii 3 CONTENTS 2.1 Introduction 2.2 FPGA 2.2.1 Overview of a general FPGA device 2.2.2 Overview of the Xilinx Spartan-3 devices 2.3 Overview of the Digilent S3 board 2.4 Development flow 2.5 Overview of the Xilinx ISE project navigator 2.6 Short tutorial on ISE project navigator 2.6.1 Create the design project and HDL codes 2.6.2 Create a testbench and perform the RTL simulation 2.6.3 Add a constraint file and synthesize and implement the code 2.6.4 Generate and download the configuration file to an FPGA device 2.7 Short tutorial on the ModelSim HDL Simulator 2.8 Bibliographie notes 2.9 Suggested experiments 2.9.1 Gate-level greater-than circuit 2.9.2 Gate-level binary decoder RT-level combinational circuit 3.1 Introduction 3.2 RT-level components 3.2.1 Relational operators 3.2.2 Arithmetic operators 3.2.3 Other synthesis-related VHDL constructs 3.2.4 Summary 3.3 Routing circuit with concurrent assignment statements 3.3.1 Conditional signal assignment statement 3.3.2 Selected signal assignment statement 3.4 Modeling with a process 3.4.1 Process 3.4.2 Sequential signal assignment statement 3.5 Routing circuit with if and case statements 3.5.1 If statement 3.5.2 Case statement 3.5.3 Comparison to concurrent statements 3.5.4 Unintended memory 3.6 Constants and generics 3.6.1 Constants 3.6.2 Generics 3.7 Design examples 3.7.1 Hexadecimal digit to seven-segment LED decoder 3.7.2 Sign-magnitude adder 11 11 11 13 13 15 17 19 21 22 22 24 27 32 33 33 33 35 35 35 37 37 38 40 41 41 44 46 46 46 47 47 49 50 52 53 53 54 56 56 59 3.8 3.9 CONTENTS 3.7.3 Barrel shifter 3.7.4 Simplified floating-point adder Bibliographic notes Suggested experiments iX 62 63 69 69 3.9.1 Multi-funetion barrel shifter 69 3.9.2 Dual-priority encoder 69 3.9.3 BCD incrementor 69 3.9.4 Floating-point greater-than circuit 70 3.9.5 Floating-point and signed integer conversion circuit 70 3.9.6 Enhanced floating-point adder 70 4 Regular Sequential Circuit 71 4.1 Introduction 71 4.1.1 D FF and register 71 4.1.2 Synchronous system 72 4.1.3 Code development 73 4.2 HDL code of the FF and register 74 4.2.1 D FF 74 4.2.2 Register 77 4.2.3 Register file 78 4.2.4 Storage components in a Spartan-3 devicexilinx speci ic 79 4.3 Simple design examples 79 4.3.1 Shift register 79 4.3.2 Binary counter and variant 81 4.4 Testbench for sequential circuits 84 4.5 Case study 88 4.5.1 LED time-multiplexing circuit 88 4.5.2 Stopwatch 96 4.5.3 FIFO buffer 100 4.6 Bibliographic notes 104 4.7 Suggested experiments 105 4.7.1 Programmable square wave generator 105 4.7.2 PWM and LED dimmer 105 4.7.3 Rotating square circuit 105 4.7.4 Heartbeat circuit 106 4.7.5 Rotating LED banner circuit 106 4.7.6 Enhanced stopwatch 106 4.7.7 Stack 106 5 FSM 107 5.1 Introduction 107 X 6 CONTENTS 5.1.1 Mealy and Moore outputs 5.1.2 FSM representation 5.2 FSM code development 5.3 Design examples 5.3.1 Rising-edge detector 5.3.2 Debouncing circuit 5.3.3 Testing circuit 5.4 Bibliographie notes 5.5 Suggested experiments 5.5.1 Dual-edge detector 5.5.2 Alternative debouncing circuit 5.5.3 Parking lot occupancy counter FSMD 6.1 Introduction 6.1.1 Single RT Operation 6.1.2 ASMD chart 6.1.3 Decision box with a register 6.2 Code development of an FSMD 6.2.1 Debouncing circuit based an RT methodology 6.2.2 Code with explicit data path components 6.2.3 Code with implicit data path components 6.2.4 Comparison 6.2.5 Testing circuit 6.3 Design examples 6.3.1 Fibonacci number circuit 6.3.2 Division circuit 6.3.3 Binary-to-BCD conversion circuit 6.3.4 Period counter 6.3.5 Accurate low-frequency counter 6.4 Bibliographie notes 6.5 Suggested experiments 6.5.1 Alternative debouncing circuit 6.5.2 BCD-to-binary conversion circuit 6.5.3 Fibonacci circuit with BCD VO: design approach 1 6.5.4 Fibonacci circuit with BCD 1/0: design approach 2 6.5.5 Auto-scaled low-frequency counter 6.5.6 Reaction timer 6.5.7 Babbage difference engine emulation circuit 107 108 111 114 114 118 122 124 124 124 124 125 127 127 127 128 129 131 132 134 136 137 138 140 140 143 147 150 153 156 157 157 157 157 157 158 158 159 PART 11 1/0 MODULES CONTENTS Xi 7 UART 163 7.1 Introduction 163 7.2 UART receiving subsystem 164 7.2.1 Oversampling procedure 164 7.2.2 Baud rate generator 165 7.2.3 UART receiver 165 7.2.4 Interface circuit 168 7.3 UART transmitting subsystem 171 7.4 Overall UART system 174 7.4.1 Complete UART core 174 7.4.2 UART verification configuration 176 7.5 Customizing a UART 178 7.6 Bibliographie notes 180 7.7 Suggested experiments 180 7.7.1 Full-featured UART 180 7.7.2 UART with an automatic baud rate detection circuit 181 7.7.3 UART with an automatic baud rate and parity detection circuit 181 7.7.4 UART-controlled stopwatch 181 7.7.5 UART-controlled rotating LED banner 182 8 PS2 Keyboard 183 8.1 Introduction 183 8.2 PS2 receiving subsystem 184 8.2.1 Physical interface of a PS2 port 184 8.2.2 Device-to-host communication protocol 184 8.2.3 Design and code 184 8.3 PS2 keyboard scan code 188 8.3.1 Overview of the scan code 188 8.3.2 Scan code monitor circuit 189 8.4 PS2 keyboard interface circuit 191 8.4.1 Basic design and HDL code 192 8.4.2 Verification circuit 194 8.5 Bibliographie notes 196 8.6 Suggested experiments 196 8.6.1 Alternative keyboard interface I 196 8.6.2 Alternative keyboard interface II 196 8.6.3 PS2 receiving subsystem with watchdog timer 197 8.6.4 Keyboard-controlled stopwatch 197 8.6.5 Keyboard-controlled rotating LED banner 197 9 PS2 Mouse 199 X11 CONTENTS 9.1 Introduction 199 9.2 PS2 mouse protocol 200 9.2.1 Basic operation 200 9.2.2 Basic initialization procedure 200 9.3 PS2 transmitting subsystem 201 9.3.1 Host-to-PS2-device communication protocol 201 9.3.2 Design and code 202 9.4 Bidirectional PS2 interface 206 9.4.1 Basic design and code 206 9.4.2 Verification circuit 208 9.5 PS2 mouse interface 210 9.5.1 Basic design 210 9.5.2 Testing circuit 212 9.6 Bibliographie notes 214 9.7 Suggested experiments 214 9.7.1 Keyboard control circuit 214 9.7.2 Enhanced mouse interface 214 9.7.3 Mouse-controlled seven-segment LED display 214 10 External SRAM 215 10.1 Introduction 215 10.2 Specification of the IS61LV25616AL SRAM 216 10.2.1 Block diagram and VO signals 216 10.2.2 Timing parameters 216 10.3 Basic memory controller 220 10.3.1 Block diagram 220 10.3.2 Timing requirement 221 10.3.3 Register file versus SRAM 222 10.4 A safe design 222 10.4.1 ASMD chart 222 10.4.2 Timing analysis 223 10.4.3 HDL implementation 224 10.4.4 Basic testing circuit 226 10.4.5 Comprehensive SRAM testing circuit 228 10.5 More aggressive design 233 10.5.1 Timing issues 233 10.5.2 Alternative design 1 234 10.5.3 Alternative design II 236 10.5.4 Alternative design III 237 10.5.5 Advanced FPGA features ilinx speci f ic 237 10.6 Bibliographie notes 240 10.7 Suggested experiments 240 CONTENTS Xiii 10.7.1 Memory with a 512K-by-16 configuration 240 10.7.2 Memory with a 1M-by-8 configuration 240 10.7.3 Memory with an 8M-by-1 configuration 240 10.7.4 Expanded memory testing circuit 241 10.7.5 Memory controller and testing circuit for alternative design 1 241 10.7.6 Memory controller and testing circuit for alternative design II 241 10.7.7 Memory controller and testing circuit for alternative design III 241 10.7.8 Memory controller with DCM 241 10.7.9 High-performance memory controller 241 11 Xilinx Spartan-3 Specific Memory 243 11.1 Introduction 243 11.2 Embedded memory of Spartan-3 device 243 11.2.1 Overview 243 11.2.2 Comparison 244 11.3 Method to incorporate memory modules 244 11.3.1 Memory module via HDL component instantiation 245 11.3.2 Memory module via Core Generator 245 11.3.3 Memory module via HDL inference 246 11.4 HDL templates for memory inference 246 11.4.1 Single-port RAM 246 11.4.2 Dual-port RAM 249 11.4.3 ROM 251 11.5 Bibliographie notes 254 11.6 Suggested experiments 254 11.6.1 Block-RAM-based FIFO 254 11.6.2 Block-RAM-based stack 254 11.6.3 ROM-based sign-magnitude adder 255 11.6.4 ROM based sin(x) function 255 11.6.5 ROM-based sin(x) and cos(x) functions 255 12 VGA controller 1: graphic 257 12.1 Introduction 257 12.1.1 Basic Operation of a CRT 257 12.1.2 VGA port of the S3 board 259 12.1.3 Video controller 259 12.2 VGA synchronization 260 12.2.1 Horizontal synchronization 260 12.2.2 Vertical synchronization 262 12.2.3 Timing calculation of VGA synchronization signals 263 12.2.4 HDL implementation 263 XIV CONTENTS 12.2.5 Testing circuit 266 12.3 Overview of the pixel generation circuit 267 12.4 Graphic generation with an object-mapped scheme 268 12.4.1 Rectangular objects 269 12.4.2 Non-rectangular object 273 12.4.3 Animated object 275 12.5 Graphic generation with a bit-mapped scheme 282 12.5.1 Dual-port RAM implementation 282 12.5.2 Single-port RAM implementation 287 12.6 Bibliographie notes 287 12.7 Suggested experiments 287 12.7.1 VGA test pattern generator 287 12.7.2 SVGA mode synchronization circuit 288 12.7.3 Visible screen adjustment circuit 288 12.7.4 Ball-in-a-box circuit 288 12.7.5 Two-balls-in-a-box circuit 289 12.7.6 Two-player pong game 289 12.7.7 Breakout game 289 12.7.8 Full-screen dot trace 289 12.7.9 Mouse pointer circuit 290 12.7.10 Small-screen mouse scribble circuit 290 12.7.11 Full-screen mouse scribble circuit 290 13 VGA Controller II: text 291 uploads/S4/ fpga.pdf