Advanced MOSFET Designs and Implications for SRAM Scaling By Changhwan Shin A d

Advanced MOSFET Designs and Implications for SRAM Scaling By Changhwan Shin A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences in the Graduate Division of the University of California, Berkeley Committee in charge: Professor Tsu-Jae King Liu, Chair Professor Borivoje Nikolić Professor Eugene E. Haller Spring 2011 Advanced MOSFET Designs and Implications for SRAM Scaling Copyright © 2011 by Changhwan Shin 1 Abstract Advanced MOSFET Designs and Implications for SRAM Scaling by Changhwan Shin Doctor of Philosophy in Engineering – Electrical Engineering and Computer Sciences University of California, Berkeley Professor Tsu-Jae King Liu, Chair Continued planar bulk MOSFET scaling is becoming increasingly difficult due to increased random variation in transistor performance with decreasing gate length, and thereby scaling of SRAM using minimum-size transistors is further challenging. This dissertation will discuss various advanced MOSFET designs and their benefits for extending density and voltage scaling of static memory (SRAM) arrays. Using three- dimensional (3-D) process and design simulations, transistor designs are optimized. Then, using an analytical compact model calibrated to the simulated transistor current-vs.-voltage characteristics, the performance and yield of six-transistor (6-T) SRAM cells are estimated. For a given cell area, fully depleted silicon-on-insulator (FD-SOI) MOSFET technology is projected to provide for significantly improved yield across a wide range of operating voltages, as compared with conventional planar bulk CMOS technology. Quasi-Planar (QP) bulk silicon MOSFETs are a lower-cost alternative and also can provide for improved SRAM yield. A more printable "notchless" QP bulk SRAM cell layout is proposed to reduce lithographic variations, and is projected to achieve six-sigma yield (required for terabit-scale SRAM arrays) with a minimum operating voltage below 1 Volt. ___________________________________ Professor Tsu-Jae King Liu, Chair Dissertation Committee Chair i To my parents for their unbounded love and support, to my brother for his sincere encouragement, and to my wife for her devoted love. ii Contents Table of Contents ii List of Figures viii List of Tables x Acknowledgements xi Table of Contents Chapter 1: Introduction ………………………......………..……………1 1.1 Static Random Access Memory (SRAM) ………………………………………..1 1.1.1 SRAM Basics ……………………………………………………………...1 1.1.2 Alternative SRAM Cell Architectures …………………………………….3 1.1.3 Sources of VT Variation ……………………………..…………………….5 1.1.3.1 Random Dopant Fluctuations (RDF) ……………………………..6 1.1.3.2 Gate Length Fluctuations …………………………………………7 1.1.3.3 Gate Work-Function Variation (WFV) …………………………...8 1.1.4 Approaches to Mitigating the Impact of VT Variation for SRAM ..…….....8 iii 1.2 Advanced Transistor Designs for the 22nm Node and Beyond ……………….…9 1.2.1 Planar Silicon-on-Insulator (SOI) MOSFETs .…………………………….9 1.2.1.1 Partially-depleted SOI (PD-SOI) MOSFET .………….………….9 1.2.1.2 fully-depleted SOI (FD-SOI) MOSFET .......………….………...10 1.2.2 Multiple-Gate MOSFETs .………………………………………………..12 1.2.2.1 Double-Gate FinFET and SOI Tri-Gate MOSFETs …………..12 1.2.2.2 Gate-All-Around (GAA) MOSFET ………………….………..13 1.3 Research Objectives and Thesis Overview …………………………………..…14 1.4 References …………………………………………………….………………...15 Chapter 2: Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22nm node …......23 2.1 Introduction ………………………………..……………………………………23 2.2 Thin-BOX FD-SOI Technology ……………………………………………......23 2.2.1 MOSFET Design Optimization …………………………………………..23 2.2.2 Impact of Random Variations ……………………………………………27 2.3 6-T SRAM Cell Performance Comparison …………………………………......28 2.3.1 Nominal Cell Design ……………………………………………………..28 iv 2.3.2 Dependency of SRAM Performance Metrics on Cell Ratio, Pull-Up Ratio, and VDD ………………………………………………………………………30 2.4 Yield-Aware SRAM Cell Design …………………………………....................31 2.4.1 Iso-Area Comparison ...…………………………………………………..32 2.4.2 Iso-Yield Comparison ...………………………………………………….33 2.4.3 Minimum Operating Voltage (Vmin) for read and write operation ....…….33 2.5 Summary ………………………..…………………………………....................34 2.6 References ………………………………….......................................................35 2.A Appendix .………………………………….......................................................37 Chapter 3: Study of Random Dopant Fluctuation (RDF) Effects for the Quasi-Planar Bulk MOSFET ……………..……...38 3.1 Introduction ………………………………..……………………………………38 3.2 Device Simulation Approach ….……………………………………………......39 3.2.1 Nominal Bulk MOSFET Designs ………………………………………..39 3.2.2 Methodology for Atomistic Device Simulation ………………………….39 3.3 Results and Discussion ….……………………………………………................42 3.3.1 Planar vs. Quasi-Planar Bulk MOSFET Designs ………………………...42 3.3.2 Body RDF vs. Source/Drain RDF …………….………………………….43 v 3.3.3 Assessment of VTH Adjustment Approaches …………………………….43 3.4 Summary ….…………………………………………….....................................45 3.5 References ….……………………………………………...................................45 Chapter 4: Full three-dimensional Simulation of 6-T SRAM Cells for the 22nm node …………………...……………..……...47 4.1 Introduction ………………………………..……………………………………47 4.2 Segmented Bulk MOSFET Structure and Fabrication Process ….……………...49 4.3 6-T SRAM Cell Designs ….………………………………………………….....49 4.4 Global and Local Variation Analysis ….………………………………………..52 4.5 Simulation of Single-Event-Upset …….………………………………………..53 4.6 Summary …….………………………………………………………………….55 4.7 References ……………………….…….………………………………………..55 Chapter 5: Quasi-Planar Bulk CMOS Technology for Improved SRAM Scalability …………..……..............58 5.1 Introduction ………………………………..……………………………………58 5.2 Device Fabrication ….……………......................................................................59 5.3 Results and Discussion ….……………................................................................61 vi 5.3.1 Quasi-Planar vs. Planar MOSFETs ………………………..……………..61 5.3.1.1 Improved Performance …………………………………………..61 5.3.1.2 Suppressed VTH Variation ……………………………………….62 5.3.1.3 Improved Short-Channel Effect …………………………………64 5.3.1.4 Increased Narrow Width Effect …………………………………65 5.3.1.5 Compact Transistor Model …..………………………………….65 5.3.1.4 Increased Narrow Width Effect …………………………………65 5.3.2 Benefits of Quasi-Planar Bulk CMOS Technology for 6-T SRAM ………67 5.3.2.1 Cell Yield Enhancement ………………………………………...67 5.3.2.2 Supply-Voltage Reduction ……………….……………………...67 5.3.1.2 Suppressed VTH Variation ……………………………………….62 5.4 Summary …….………………………………………………………………….68 5.5 References ……………………….…….………………………………………..69 Chapter 6: Performance and Yield Benefits of Quasi-Planar Bulk CMOS Technology for 6-T SRAM at the 22 nm Node ………….71 6.1 Introduction ………………………………..……………………………………71 6.2 Quasi-Planar Bulk Technology ….……………...................................................73 6.2.1 Optimized MOSFET Performance ………………………..……….73 vii 6.2.2 Impact of Random and Systematic Variations …………………….75 6.3 Notchless 6-T SRAM Cell Designs ….……………............................................77 6.4 SRAM Yield Estimation ….…………….............................................................81 6.4.1 Iso-Area and Iso-Yield Comparisons between Planar and Quasi-Planar Bulk Cell Designs …………….81 6.4.2 Notchless Quasi-Planar Bulk SRAM Cell Yield …………………82 6.5 Summary …….………………………………………………………………….83 6.6 References ……………………….…….………………………………………..83 Chapter 7: Conclusion ……………………………………….…………87 7.1 Contribution of This Work ………………………………..…………………….87 7.2 Suggested Future Work ….……………...............................................................90 A. Improved Manufacturability ………………..………..……….91 B. Independent Biasing Transistors ………………………..……92 C. Compatibility with Advanced Device Architecture ………….92 7.3 References ……………………….…….………………………………………..93 viii List of Figures 1.1 Circuit schematic for a six-transistor (6-T) SRAM cell 2 1.2 Definition of the static noise margin and write-ability current 3 1.3 Alternative SRAM bit-cell architecture 4 1.4 Standard deviation of threshold voltage vs. channel length 5 1.5 Randomly distributed dopant atoms in an n-channel MOSFET 6 1.6 Illustration of a nano-scale MOSFET showing line-edge-roughness 7 1.7 Illustration of hypothetical metal gate film 8 1.8 Transmission electron micrograph image of a PD-SOI n-MOSFET with HK/MG 9 1.9 Product design compromises for planar bulk, PD-SOI, and FD-SOI 10 1.10 Experimental data for SOI layer thickness variation 11 1.11 FD-SOI technology features 12 1.12 Transmission electron micrograph image of FinFET structures 13 1.13 Transmission electron micrograph image of Omega-/Tri-gate MOSFET structures 13 1.14 Transmission electron micrograph image of twin silicon nanowire MOSFET 14 2.1a Cross-sectional view of a thin-BOX FD-SOI MOSFET structure 24 2.1b Experimental data for SOI thickness variation 25 2.2 Transfer characteristics of planar bulk and FD-SOI MOSFETs 26 2.3 Simulated I-V curves of pull-down transistor for LER/RDF 26 2.4 Comparisons of SNM and write current 29 2.5 Comparison of SRAM cell performance metrics 30 2.6 Impact of VDD scaling on 6-T SRAM cell performance metrics 31 2.7 Yield of Iw vs. Yield of SNM for FD-SOI and planar bulk 32 2.8 Yield of Iw vs. Yield of SNM for FD-SOI and enlarged planar bulk 33 2.9 Dependence of yield on VDD 34 3.1 3D bird-eye view and cross-sectional view of the quasi-planar bulk MOSFET 39 3.2 Example of a QP bulk MOSFET with atomistic doping profiles and isometric view 40 3.3 Simulated I-V curves for planar and QP bulk MOSFETs with atomistic doping 41 3.4 Comparison of body RDF vs. source/drain RDF effects 43 3.5 Impact of nominal VTH adjustment on VTH variation 44 4.1a Cross-sectional views of a two-striped SegFET 48 4.1b Front-end-of-line fabrication process steps for a SegFET 48 ix 4.2 6T-SRAM cell area scaling trend 49 4.3 3D 6-T SRAM cells simulation results 50 4.4 3D 6T-SRAM cell structures with fine meshing 51 4.5 SNM and Iw vs. VDD 52 4.6 SegFET vs. planar MOSFET comparison 53 4.7 Heavy ion beam modeling 54 4.8 Transient simulations of heavy-ion-beam strike on the high storage node 54 5.1 Sequence of front-end-of-line CMOS fabrication process steps for QP MOSFET 60 5.2a 0.149μm2 SRAM cell plan-view CDSEM image after gate patterning 60 5.2b XTEM taken along a poly-Si gate electrode in an SRAM array 60 5.3 Comparison of ON/OFF current statistics for planar vs. QP MOSFETs 61-62 5.4 Comparison of saturation VTH statistics for planar vs. QP MOSFETs 63 5.5 Pelgrom plots for NMOS and PMOS logic devices 64 5.6 Saturation threshold voltage with decreasing gate length 64 5.7 Measured reverse narrow width effect for devices with 36nm gate length 65 5.8 Comparison of measured and modeled output characteristics 66 5.9 Sigma and 3-sigma/median values for SNM and WRM 67 5.10 Degradation in 3-sigma/median for SNM and WRM 68 6.1 Bird-eye view of a quasi-planar bulk MOSFET and along/across the channel 72 6.2 Simulated transfer characteristics for planar and quasi-planar bulk MOSFETs 73 6.3 Simulated VTH,SAT for planar bulk vs. quasi-planar bulk MOSFETs 76 6.4 Half-bit cell layouts for notched and notchless SRAM cell designs 78 6.5 3-D 6-T SRAM cell simulation results 79 6.6a SRAM cell read current 80 6.6b PD device gate capacitance 80 6.6c Pseudo-transient simulation of the storage-node voltage during a write operation 80 6.7 SRAM cell sigma comparisons for SNM and IW 82 6.8 SRAM cell sigma comparisons for SNM and IW 82 7.1a Proposed new layout of the 6-T SRAM bit-cell 91 7.1b Circuit schematic of the 6-T SRAM bit-cell with external voltage skews 91 7.2 Conventional layout of a 6-T SRAM bit-cell uploads/Ingenierie_Lourd/ cshin-001-042.pdf

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