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1 THÈSE Pour obtenir le grade de DOCTEUR DE LA COMMUNAUTE UNIVERSITE GRENOBLE A

1 THÈSE Pour obtenir le grade de DOCTEUR DE LA COMMUNAUTE UNIVERSITE GRENOBLE ALPES préparée dans le cadre d’une cotutelle entre la Communauté Université Grenoble Alpes et l’Université Aristote de Thessalonique Spécialité : Nanoélectronique et nanotechnologies Arrêté ministériel : le 6 janvier 2005 - 7 août 2006 Présentée par Théano KARATSORI Thèse dirigée par Prof. Gérard GHIBAUDO et codirigée par Prof. Charalabos DIMITRIADIS préparée au sein de l’IMEP-LAHC et de l’Université Aristote de Thessalonique dans l'École Doctorale d’Électronique, Électrotechnique, Automatique et Traitement du Signal Caractérisation et modélisation de UTBB MOSFET sur SOI pour les technologies CMOS avancées et applications en simulations circuits Thèse soutenue publiquement le 12 Juillet 2017, devant le jury composé de : Francis BALESTRA Directeur de recherche CNRS Alpes, Président Brice GAUTIER Professeur, INSA-Lyon, Rapporteur Nathalie MALBERT Professeur, Université de Bordeaux, Rapporteur Spyridon NIKOLAIDIS Professeur, Université Aristote de Thessalonique, Examinateur Dimitrios TASSIS Professeur Associé, Université Aristote de Thessalonique, Examinateur Charalabos DIMITRIADIS Professeur, Université Aristote de Thessalonique, invité Gérard GHIBAUDO Directeur de recherche CNRS Alpes, invité 2 3 THESIS For the degree of DOCTOR OF PHILOSOPHY OF THE UNIVERSITY GRENOBLE ALPES prepared under a co-supervision between the University Grenoble Alpes and the Aristotle University of Thessaloniki Specialty : Nanoelectronics and nanotechnologies Ministerial Order : 6 January 2005 - 7 August 2006 Presented by Theano KARATSORI Thesis directed by Prof. Gérard GHIBAUDO and Co-directed by Prof. Charalabos DIMITRIADIS prepared in the laboratory IMEP-LAHC and the Aristotle University of Thessaloniki in the École Doctorale d’Électronique, Électrotechnique, Automatique et Traitement du Signal Electrical characterisation and modeling of advanced nano-scale ultra-thin body and burried oxide (UTBB) MOSFETs and applications in circuit simulations Thesis defended in public on the 12 Juillet 2017, in front of the jury composed of : Francis BALESTRA Research director CNRS Alpes, President Brice GAUTIER Professor, INSA-Lyon, Rapporteur Nathalie MALBERT Professor, University of Bordeaux, Rapporteur Spyridon NIKOLAIDIS Professor, Aristotle University of Thessaloniki, Examiner Dimitrios TASSIS Associate Professor, Aristotle University of Thessaloniki, Examiner Charalabos DIMITRIADIS Professor, Aristotle University of Thessaloniki, invited Gérard GHIBAUDO Research director CNRS Alpes, invited 4 5 Abstract The progressive down-scaling of CMOS technology has driven the semiconductor industry to the realization of faster and lower power consumption VLSI circuits and systems. Among the most common solutions for high performance nano-scale area devices are the fin- shaped field-effect transistors (FinFETs) and the fully-depleted silicon-on-insulator (FDSOI) MOSFETs, which can provide a high immunity to the short-channel effects (SCEs), low threshold voltage variability and an improved drain-induced barrier lowering level (DIBL). Compared to FinFET, the UTBB FDSOI technology utilizes a much simpler fabrication process thanks to its planar structure. Furthermore, its back-gate bias option makes it particularly interesting for multi-Vt applications. The present thesis is dealing with issues arising from the scaling of new-era devices in the modern MOSFET design: the development of an analytical and compact drain current model, valid from weak to strong inversion, describing accurately the transfer and output characteristics of short-channel FDSOI devices and the investigation of performance issues - namely reliability and variability issues- of such advanced nano-scale transistors. Meanwhile, the accurate determination of the MOSFET electrical parameters is also essential for understanding the physics and engineering of the devices, particularly if we take into account that as the supply voltage is reduced with device scaling, the operating gate bias moves closer to the threshold voltage (near threshold operation), and the assumption that the inversion charge varies approximately linearly with gate voltage overdrive becomes less and less accurate. Thus, an additional goal is the development of a methodology which allows the extraction of MOSFET parameters over the full gate voltage range i.e. from weak to strong inversion region, enabling to fully capture the transition between subthreshold and above threshold region, despite the reduction of supply voltage. First, we present a new full gate voltage range methodology using a Lambert W function based inversion charge model, for extracting the electrical parameters in FDSOI nano-MOSFET devices. Split capacitance-voltage measurements carried out on 14 nm technology FDSOI devices show that the inversion charge variation with gate voltage can be well described by the Lambert W function. Based on the drain current equation in the linear region including the inversion charge described by the Lambert function of gate voltage and the standard mobility equation enables the extraction of five electrical MOSFET parameters from experimental transfer characteristics (ideality factor, threshold voltage, low field mobility, first and second order mobility attenuation factors). The extracted parameters were compared with those extracted by the well-known Y-function in strong inversion region. The present methodology for extracting the electrical MOSFET parameters has been verified over a wide range of channel lengths and back gate voltages on nano-scale FDSOI devices, demonstrating its simplicity, accuracy and robustness. Second, we have derived simple expressions for the minimum value of the front and back gate surface potentials with which we have developed analytical models for the respective threshold voltages and ideality factors with back gate control of lightly doped short channel UTBB FDSOI MOSFETs. The threshold voltage and ideality factor models of the front and back gates have been verified with numerical simulations in terms of the device geometry parameters and the applied bias voltages, as well as with experimental results for devices with channel length down to 17 nm. Based on these models we have developed an analytical drain current compact model for lightly doped short-channel UTBB FDSOI 6 MOSFETs with back gate control. The model, which includes the effects of drain-induced barrier lowering, channel-length modulation, saturation velocity, mobility degradation, quantum confinement, velocity overshoot and self-heating, has been validated by comparing with experimental transfer and output characteristics of various devices and back-bias conditions. The good accuracy of the model makes it suitable for implementation in circuit simulation tools. Indeed, the drain current compact model is implemented via Verilog-A code for simulation of fundamental circuits in circuit simulators. Following the drain current compact model development, reliability issues including hot-carrier injection (HCI) and negative bias temperature instability (NBTI) are discussed for these nano-scale UTBB FDSOI MOSFETs. The hot-carrier effect, which occurs near the drain end due to hot carriers accelerated in the channel, is prominent in n-MOS devices, while the NBTI is prominent in p-MOS devices along the entire channel when negative gate-to- source voltage is applied.  In our analysis, the hot-carrier (HC) induced traps are investigated by low- frequency noise (LFN) measurements in the frequency and time domain. The measured noise spectra are composed of 1/f and Lorentzian-type components. The Lorentzian noise is due either to generation-recombination noise or to random telegraph noise (RTN). Based on the LFN results, the effect of the HC-stress on FDSOI MOSFETs is investigated after short and long-time stress. Analysis of RTN traps detected in fresh and HC-stressed devices indicate that the RTN amplitude is uncorrelated to the trap time constants, i.e. the impact of the trap depth from the interface is masked by that of the trap location over the channel. The overall results lead to an analytical expression for the RTN amplitude, enabling to predict the RTN changes from the subthreshold to the above threshold region. After we identified the degradation mechanisms and based on our analytical compact drain current compact model, we developed a semi-empirical aging hot-carrier model predicting with good accuracy the device degradation stressed under different bias conditions using a unique set of model parameters.  Concerning the NBTI phenomenon, the threshold voltage shifts during stress at different temperatures and gate bias voltage conditions show that the NBTI is dominated by trapping of holes in pre-existing traps of the gate dielectric, while the recovery transient follows a logarithmic-like time dependence. In this way, we have developped an NBTI model capturing the temperature and gate voltage dependence in such UTBB FDSOI p-MOSFETs with zero back gate bias and small drain bias voltage. Finally, the last part of our research work which is covering a significant part of the thesis, deals with the local variability phenomenon in advanced nano-scale devices. The main sources of drain and gate current local variability have been thoroughly studied. In this aspect, we developed a fully functional drain current mismatch model, valid for any gate and drain bias condition, including all main sources of drain current local variability assumed to be uncorrelated, namely the threshold voltage, the current gain factor, the source-drain series resistance and the subthreshold slope ideality factor mismatches. Concerning the gate current local variability modeling the local fluctuations of the threshold voltage and the gate oxide thickness were taken into account. The proposed models for the drain and gate current mismatch were verified, using a Lambert function based compact model and performing 7 Monte Carlo simulations that reproduce accurately the experimentally measured current variations. Then, owing to the proposed mismatch models, we characterized various advanced technologies in terms of local and global variability performance. Indeed, a detailed statistical characterization of drain current local and global variability in 14 nm Si bulk FinFET devices and in sub 15 nm gate length Si/SiGe trigate nanowire p-MOSFETs is performed. To this end, we extracted uploads/Litterature/ karatsori-2017-archivage.pdf