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ADV7511 Low-Power HDMI 1.4 Compatible Transmitter with Audio Return Channel PRO

ADV7511 Low-Power HDMI 1.4 Compatible Transmitter with Audio Return Channel PROGRAMMING GUIDE - Revision G– March 2012 PROGRAMMING GUIDE ADV7511 Page 2 of 203 Rev G REVISION HISTORY Rev. 0: Initial Release Rev A: Section Change Description Section▶4.3.2.1 Corrected register bit information for the “Input Style” bit Sections▶4.3.4, ▶4.4.1.3, ▶4.4.1.4, and▶4.4.1.5 Clarified that automatic pixel repeat does not work with HBR, DSD, or DST audio inputs. Rev B: Section Change Description Section ▶4.3.10 Added 3D section. Section ▶4.3.8 Updated CSC Tables. Section▶4.8 Updated reset information. Section ▶4.9 Updated CEC Timing Charts. Rev C: Section Change Description Section 5 - Corrected recommended settings for fixed registers 0x98, 0x9C, 0x9D, 0xA2, and 0xA3. Rev D: Section Change Description Section ▶4.3.8 Added additional CSC Tables Removed “confidential” statements Rev E: Section Change Description Section ▶4.3.8 Added additional CSC Tables Rev F: Section Change Description Section ▶4.7.1 Error controller register address corrected Section ▶Section 5 - Changed chip revision to 12 Rev G: Section Change Description Section ▶4.3.8 Corrected CSC Tables 53 and 54 PROGRAMMING GUIDE ADV7511 Page 3 of 203 Rev G TABLE OF CONTENTS Revision History ........................................................................................................................................................................................................................................2 Section 1 - Introduction ........................................................................................................................................................................................................................ 12 1.1 Scope and Organization ...................................................................................................................................................................................................... 12 1.1.1 Organization ................................................................................................................................................................................................................. 12 1.1.2 Use of Register Bits ...................................................................................................................................................................................................... 12 1.1.3 Register Types ............................................................................................................................................................................................................... 12 1.1.4 Format Standards ......................................................................................................................................................................................................... 12 1.1.5 Links ............................................................................................................................................................................................................................... 12 1.1.6 Symbols .......................................................................................................................................................................................................................... 13 Section 2 - References ............................................................................................................................................................................................................................ 14 2.1 ADI Documents ................................................................................................................................................................................................................... 14 2.2 Specifications ........................................................................................................................................................................................................................ 14 Section 3 - Quick Start Guide ............................................................................................................................................................................................................... 15 Section 4 - Programming Tasks ............................................................................................................................................................................................................ 16 4.1 I2C Bus .................................................................................................................................................................................................................................. 16 4.2 General Control ................................................................................................................................................................................................................... 17 4.2.1 Hot Plug Detect (HPD) and Monitor Sense ............................................................................................................................................................. 17 4.2.2 HDMI DVI Selection ................................................................................................................................................................................................... 19 4.2.3 AV Mute ........................................................................................................................................................................................................................ 19 4.2.4 TMDS Power-Down .................................................................................................................................................................................................... 20 4.2.5 Packet Update ............................................................................................................................................................................................................... 21 4.2.6 Source Product Description (SPD) Packet ............................................................................................................................................................... 22 4.2.7 Spare Packets ................................................................................................................................................................................................................. 23 4.2.8 System Monitoring ....................................................................................................................................................................................................... 24 4.2.8.1 DDC Controller Status ................................................................................................................................................................ 24 4.2.8.2 HDCP/EDID Controller Error Codes ...................................................................................................................................... 25 4.2.9 Fixed Registers That Must Be Set .............................................................................................................................................................................. 26 4.3 Video Setup ........................................................................................................................................................................................................................... 26 4.3.1 Input Formatting .......................................................................................................................................................................................................... 26 4.3.2 Video Input Tables ....................................................................................................................................................................................................... 27 4.3.2.1 Input Data Clock .......................................................................................................................................................................... 40 4.3.3 Video Mode Detection ................................................................................................................................................................................................ 44 4.3.4 Pixel Repetition ............................................................................................................................................................................................................ 48 4.3.5 422 444 Conversion ..................................................................................................................................................................................................... 51 4.3.6 Deep Color Conversion .............................................................................................................................................................................................. 52 4.3.7 DE, Hsync and Vsync Generation ............................................................................................................................................................................. 52 PROGRAMMING GUIDE ADV7511 Page 4 of 203 Rev G 4.3.7.1 DE generation ............................................................................................................................................................................... 54 4.3.7.2 Hsync and Vsync Generation ..................................................................................................................................................... 54 4.3.7.3 Hsync and Vsync Adjustment .................................................................................................................................................... 54 4.3.7.4 DE, Hsync, and Vsync Generation Recommended Settings .................................................................................................. 55 4.3.8 Color Space Converter (CSC) .................................................................................................................................................................................... 59 4.3.8.1 Color Space Conversion (CSC) Matrix ..................................................................................................................................... 60 4.3.8.2 Color Space Converter (CSC) Special Features ....................................................................................................................... 68 4.3.8.3 Changing the Color Space with Active Display ....................................................................................................................... 68 4.3.9 Video InfoFrame and Other Video Related Packets ............................................................................................................................................... 70 4.3.9.1 AVI InfoFrame ............................................................................................................................................................................. 71 4.3.9.2 MPEG InfoFrame ........................................................................................................................................................................ 74 4.3.9.3 Gamut Metadata Packet .............................................................................................................................................................. 77 4.3.10 3D Video Setup ............................................................................................................................................................................................................. 80 4.3.10.1 VIC ................................................................................................................................................................................................. 80 4.3.10.2 Pixel Repeat ................................................................................................................................................................................... 80 4.3.10.3 Vendor Specific InfoFrame ......................................................................................................................................................... 81 4.4 Audio Setup .......................................................................................................................................................................................................................... 82 4.4.1 Input Format ................................................................................................................................................................................................................. 82 4.4.1.1 Inter-IC Sound (I2S) Audio ....................................................................................................................................................... 85 4.4.1.2 Sony/Philips Digital Interface (SPDIF) Audio ........................................................................................................................ 88 4.4.1.3 Direct Stream Digital (DSD) Audio .......................................................................................................................................... 89 4.4.1.4 High Bit-Rate (HBR) Audio ....................................................................................................................................................... 90 4.4.1.5 Direct Stream Transfer (DST) Audio ....................................................................................................................................... 92 4.4.2 N and CTS ..................................................................................................................................................................................................................... 93 4.4.2.1 N Parameter .................................................................................................................................................................................. 93 4.4.2.2 CTS Parameter ............................................................................................................................................................................. 94 4.4.2.3 Recommended N and Expected CTS Values ........................................................................................................................... 94 4.4.3 Audio Sample Packets.................................................................................................................................................................................................. 95 4.4.3.1 Details for I2S Channel Status .................................................................................................................................................... 96 4.4.4 Audio InfoFrame ........................................................................................................................................................................................................ 100 4.4.5 Audio Content Protection (ACP) Packet ................................................................................................................................................................ 103 4.4.6 International Standard Recording Code (ISRC) Packet ....................................................................................................................................... 105 4.5 Audio Return Channel (ARC) ......................................................................................................................................................................................... 108 4.5.1 ARC Configuration.................................................................................................................................................................................................... 108 4.6 EDID Handling .................................................................................................................................................................................................................. 109 4.6.1.1 EDID Definitions ....................................................................................................................................................................... 109 PROGRAMMING GUIDE ADV7511 Page 5 of 203 Rev G 4.6.1.2 Additional Segments .................................................................................................................................................................. 109 4.6.1.3 EDID Tries Register (0xC9 [3:0]) ........................................................................................................................................... 110 4.6.1.4 EDID Reread Register (0xC9[4]) ............................................................................................................................................ 110 4.7 HDCP Handling ................................................................................................................................................................................................................ 111 4.7.1 For One Sink and No Upstream Devices ................................................................................................................................................................ 111 4.7.2 For Multiple Sinks and No Upstream Devices ....................................................................................................................................................... 111 4.7.3 For Use in a Repeater ................................................................................................................................................................................................. 112 4.7.4 Software Implementation .......................................................................................................................................................................................... 112 4.7.5 AV Mute ...................................................................................................................................................................................................................... 113 4.7.6 HDCP Delay Control ................................................................................................................................................................................................ 113 4.8 Power Management ........................................................................................................................................................................................................... 117 4.8.1 Main Power-Down ..................................................................................................................................................................................................... 117 4.8.2 Additional Power Down Methods ........................................................................................................................................................................... 118 4.9 CEC Processing .................................................................................................................................................................................................................. 119 4.9.1 CEC Addressing ......................................................................................................................................................................................................... 120 4.9.2 CEC Transmitter ........................................................................................................................................................................................................ 120 4.9.2.1 CEC Transmitter Setup and Control ....................................................................................................................................... 121 4.9.2.2 CEC Transmitter Interrupt Handling ...................................................................................................................................... 121 4.9.3 CEC Receiver .............................................................................................................................................................................................................. 124 4.9.3.1 CEC Receiver Setup and Control ............................................................................................................................................. 124 4.9.3.2 CEC Receiver Message Processing and Interrupt Handling ................................................................................................ 124 4.9.3.3 Handling CEC Initiators with non-compliant EOM ............................................................................................................. 128 4.9.4 Typical Operation Flow ............................................................................................................................................................................................. 133 4.9.4.1 CEC Acting as an Initiator: ....................................................................................................................................................... 133 4.9.4.2 CEC Acts as a Follower: ............................................................................................................................................................ 134 4.9.5 CEC System Control .................................................................................................................................................................................................. 134 4.9.6 CEC System Power and CDC Control .................................................................................................................................................................... 134 4.9.7 CEC Timing Control ................................................................................................................................................................................................. 134 4.10 HDCP/EDID Controller ................................................................................................................................................................................................... 143 4.10.1 ADV7511 EDID/HDCP Support Features ............................................................................................................................................................. 143 4.11 Interrupt Handling ............................................................................................................................................................................................................ 144 4.11.1 Wake Up Opcodes ..................................................................................................................................................................................................... 145 4.11.2 Hot Plug Detect .......................................................................................................................................................................................................... 145 4.11.3 Monitor Sense ............................................................................................................................................................................................................. 145 4.11.4 Active Vsync Edge ..................................................................................................................................................................................................... 145 4.11.5 Audio FIFO Full ......................................................................................................................................................................................................... 146 4.11.6 Embedded Sync Parity Error .................................................................................................................................................................................... 146 PROGRAMMING GUIDE ADV7511 Page 6 of 203 Rev G 4.11.7 EDID Ready ................................................................................................................................................................................................................ 146 4.11.8 HDCP Authenticated ................................................................................................................................................................................................ 146 4.11.9 HDCP Error ................................................................................................................................................................................................................ 146 4.11.10 BKSV Flag ............................................................................................................................................................................................................... 146 4.11.11 CEC Tx Ready Flag ............................................................................................................................................................................................... 146 4.11.12 CEC Tx Arbitration Lost Flag .............................................................................................................................................................................. 146 4.11.13 CEC Tx Retry Timeout Flag ................................................................................................................................................................................ 146 4.11.14 CEC Rx Ready Flags .............................................................................................................................................................................................. 146 Section 5 - Register Maps .................................................................................................................................................................................................................... 153 PROGRAMMING GUIDE ADV7511 Page 7 of 203 Rev G TABLE OF FIGURES Figure 1 Packet Update....................................................................................................................................................................................................................... 22 Figure 2 2X Clock timing ................................................................................................................................................................................................................... 34 Figure 3 DDR DE timing - Register 0x16[1] = 1 ............................................................................................................................................................................ 40 Figure 4 DDR DE timing - Register 0x16[1] = 0 ............................................................................................................................................................................ 40 Figure 5 Input Clock Divide Control ............................................................................................................................................................................................... 41 Figure 6 Sync Processing Block Diagram ........................................................................................................................................................................................ 53 Figure 7 Active Video ......................................................................................................................................................................................................................... 54 Figure 8 Hsync Reconstruction ......................................................................................................................................................................................................... 55 Figure 9 Vsync Reconstruction (centered) ...................................................................................................................................................................................... 55 Figure 10 Sync Adjustment Vsync Offset (centered) ................................................................................................................................................................... 55 Figure 11 Single CSC channel .......................................................................................................................................................................................................... 60 Figure 12 I2C Write Timing of GMP Data ..................................................................................................................................................................................... 78 Figure 13 IEC60958 Sub-Frame ....................................................................................................................................................................................................... 85 Figure 14 Sub-Frame Format for ADV7511 .................................................................................................................................................................................. 86 Figure 15 Standard I2S Timing ........................................................................................................................................................................................................ 86 Figure 16 Right-Justified Timing ..................................................................................................................................................................................................... 86 Figure 17 Left-Justified Timing ........................................................................................................................................................................................................ 87 Figure 18 AES3 Direct Timing ......................................................................................................................................................................................................... 87 Figure 19 I2S 32 Bit Mode Timing .................................................................................................................................................................................................. 87 Figure 20 32 Bit Mode Left- or Right-Justified Timing ................................................................................................................................................................ 88 Figure 21 DST Timing ....................................................................................................................................................................................................................... 92 Figure 22 Audio Clock Regeneration .............................................................................................................................................................................................. 93 Figure 23 Definition of Channel Status Bits 20 to 23 ................................................................................................................................................................... 98 Figure 24 ARC Hardware Configuration ..................................................................................................................................................................................... 108 Figure 25 Reading EDID through the ADV7511 ........................................................................................................................................................................ 110 Figure 26 HDCP Software Implementation................................................................................................................................................................................. 114 Figure 27 Typical All-HDMI Home Theatre ............................................................................................................................................................................... 120 Figure 28 CEC Transmitter State Machine .................................................................................................................................................................................. 121 Figure 29 CEC Receiver Timestamp Operation – Message Arrival ......................................................................................................................................... 125 Figure 30 CEC Receiver Timestamp Operation – Partial Message Processing ...................................................................................................................... 126 Figure 31 CEC Receiver Timestamp Operation – New Message Arrival ................................................................................................................................ 127 Figure 32 CEC Receiver State Machine ........................................................................................................................................................................................ 128 Figure 33 ADV7511 EDID and DDC Controller Functional Flow .......................................................................................................................................... 144 Figure 34 Interrupt Handling ......................................................................................................................................................................................................... 147 Figure 35 Interrupt Handling Example ........................................................................................................................................................................................ 148 PROGRAMMING GUIDE ADV7511 Page 8 of 203 Rev G TABLE OF TABLES Table 1 I2C Bus Related Registers (Main Map) ............................................................................................................................................................................. 16 Table 2 Hot Plug Detect (HPD) and Monitor Sense Related Registers (Main Map) ............................................................................................................... 18 Table 3 Hot Plug Detect (HPD) and Monitor Sense Related Registers (CEC Map) ................................................................................................................ 19 Table 4 HDMI DVI Selection Related Registers (Main Map) ..................................................................................................................................................... 19 Table 5 AV Mute Related Registers (Main Map) ........................................................................................................................................................................... 20 Table 6 TMDS Power-Down Related Registers (Main Map) ...................................................................................................................................................... 21 Table 7 Source Product Description (SPD) Packet Related Registers (Main Map) ................................................................................................................. 23 Table 8 Source Product Description (SPD) Packet Related Registers (Packetmemory Map) ................................................................................................ 23 Table 9 Spare Packets Related Registers (Main Map) ................................................................................................................................................................... 24 Table 10 Spare Packets Related Registers (Packetmemory Map) .............................................................................................................................................. 24 Table 11 DDCController Status ..................................................................................................................................................................................................... 25 Table 12 Error Code Definitions .................................................................................................................................................................................................... 25 Table 13 System Monitoring Related Registers (Main Map) ...................................................................................................................................................... 26 Table 14 Fixed Registers That Must Be Set (Main Map) ............................................................................................................................................................ 26 Table 15 Input ID Selection ............................................................................................................................................................................................................ 27 Table 16 Normal RGB or YCbCr 4:4:4 (36, 30, or 24 bits) with Separate Syncs; Input ID = 0 ............................................................................................. 27 Table 17 YCbCr 4:2:2 Formats (24, 20, or 16 bits) Input Data Mapping: 0x48[4:3] = ‘10’ (left justified) Input ID = 1 or 2 ........................................... 28 Table 18 YCbCr 4:2:2 Formats (24, 20, or 16 bits) Input Data Mapping: 0x48[4:3] = ‘01’ (right justified) Input ID = 1 or 2 ........................................ 29 uploads/Management/ adv7511-programming-guide.pdf