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Reference guide 3 BluespecTM SystemVerilog Reference Guide Revision June Copyright c ?? Bluespec Inc All rights reserved CReference Guide Bluespec SystemVerilog Trademarks and copyrights Verilog is a trademark of IEEE the Institute of Electrical and Elect

BluespecTM SystemVerilog Reference Guide Revision June Copyright c ?? Bluespec Inc All rights reserved CReference Guide Bluespec SystemVerilog Trademarks and copyrights Verilog is a trademark of IEEE the Institute of Electrical and Electronics Engineers The Verilog standard is copyrighted owned and maintained by IEEE VHDL is a trademark of IEEE the Institute of Electrical and Electronics Engineers The VHDL standard is copyrighted owned and maintained by IEEE SystemVerilog is a trademark of Accellera Inc The SystemVerilog standard is owned and maintained by Accellera Bluespec is a trademark of Bluespec Inc AzureIP is a trademark of Bluespec Inc CBluespec SystemVerilog Reference Guide Contents Table of Contents Introduction Meta notation Lexical elements Whitespace and comments Identi ?ers and keywords Integer literals Type conversion of integer literals Real literals Type conversion of real literals String literals Don ? t-care values Compiler directives File inclusion ? include and ? line Macro de ?nition and substitution ? de ?ne and related directives Conditional compilation ? ifdef and related directives Packages and the outermost structure of a BSV design Scopes name clashes and quali ?ed identi ?ers The Standard Prelude package AzureIPTM Foundation Libraries Types Polymorphism Provisos brief intro The pseudo-function valueof or valueOf A brief introduction to deriving clauses Modules and interfaces and their instances Explicit state via module instantiation not variables Interface declaration Subinterfaces Module de ?nition Module and interface instantiation Short form instantiation CReference Guide Bluespec SystemVerilog Long form instantiation Interface de ?nition de ?nition of methods Shorthands for Action and ActionValue method de ?nitions De ?nition of subinterfaces De ?nition of methods and subinterfaces by assignment Rules in module de ?nitions Examples Synthesizing Modules Type Polymorphism Module Interfaces and Arguments Static and dynamic semantics Static semantics Type checking Proviso checking and bit-width constraints Static elaboration Dynamic semantics Reference semantics Mapping into e ?cient parallel clocked synchronous hardware How rules are chosen to ?re Mapping speci ?c hardware models User-de ?ned types type de ?nitions Type synonyms Enumerations Structs and tagged unions Variable declarations and statements Variable and array declaration and initialization Variable assignment Implicit declaration and initialization Register reads and writes Registers and square-bracket notation Registers and range notation Registers and struct member selection Begin-end statements Conditional statements Loop statements CBluespec SystemVerilog Reference Guide While loops For loops Function de ?nitions De ?nition of functions by assignment Function types Expressions Don ? t-care expressions Conditional expressions Unary and binary operators Bit concatenation and selection Begin-end expressions Actions and action blocks Actionvalue blocks Function calls Method calls Static type assertions Struct and union expressions Struct expressions Struct member selection Tagged union expressions Tagged union member selection Interface expressions Di ?erences between interfaces and structs Rule expressions Pattern matching Case statements with pattern matching Case expressions with pattern matching Pattern matching in if statements and other contexts Pattern matching assignment statements Finite state machines CReference Guide Bluespec SystemVerilog Important primitives The types bit and Bit Bit-width compatibility UInt Int int and Integer String Tuples Registers FIFOs FIFOFs System tasks and functions Displaying information format