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Programming with bluespec systemverilog design methodologies styles patterns and examples

Programming with Bluespec SystemVerilog Design Methodologies Styles Patterns and Examples Preliminary Draft Please do not circulate without permission from Bluespec Inc Revision November Copyright c ?? Bluespec Inc This document describes Bluespec SystemVerilog coding guidelines though a series of descriptions and examples where the objectives are to ? bring experienced Verilog and VHDL designers up to speed with the abilities and features of Bluespec ? produce expected RTL with respect to interfaces and structures ? take advantage of the extensive libraries provided by Bluespec This document is organized into several sections which need not be read in sequence Rather each section gives hints advice and examples on particular design or programming structures This document is not intended to replace the Reference Guide or the User ? s guide It is a intended only as a supplement to aid designers in expressing their designs in the Bluespec environment This document is under development CContents Table of Contents Types Bit Types Non Bit Types Conversion Between Types Types from the Bluespec Library Designing Interfaces Interface Basics Sharing Signals in an Interface Combining Interfaces Basic Interfaces from the Bluespec Library Interface Paradigms from the Library Logic Representation Sequential Element Combinational Logic System Design Examples Synchronous State Machine De ?ning Interface Methods Extracting pieces from an interface Using RWire to Avoid Registers and Latency Testbenches Controlling Simulation Stored Test Patterns Generating Random Test Patterns Common Hints and Style Suggestions Identi ?er Names Use let Variables Using types instead of ? de ?nes Adding Monitors C Helping the Scheduler Rules versus Always Blocks Alleviating Read Write Con icts with Con ?gReg Register Updates Debugging Hints and Tips Viewing Complex Data Structures BlueSim Improving Simulation Speed Other Notes Using Bluespec with other tools Using Existing Verilog Components in a BSV Design Sample Verilog Memory Import C Types Bluespec provides a strong static type-checking environment Everything has a type that is every variable and every expression has a type Variables must be assigned values which have compatible types Type checking which occurs before program elaboration or execution ensures that object types are compatible and that needed conversion functions are valid for the context This section describes common types and structures as de ?ned and used in the Bluespec environment Bit Types At the lowest level synthesizable objects can be considered as a wire or wires having some ?xed width and interpretation These correspond to Verilog wire and reg and additionally have tighter semantics surrounding their use ? Bool is a Boolean ?? a True or False value The implementation is one bit but bit-wise operations on Booleans in Bluespec are illegal Booleans should be used for True or False values Bit should be used for zero or one variables ? Bit n de ?nes a type containing n bits Type Bit allows bit-wise operations but Bit cannot be used as a Bool that is operators and are not allowed Use Bit n types for variables which are simple bit patterns Note bit is a synonym for Bit