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Tcl guide 1 Leda Tcl Interface Guide Version J- December Comments E- mail your comments about this manual to leda-support synopsys com CCopyright Notice and Proprietary Information Copyright ? Synopsys Inc All rights reserved This software and documentati

Leda Tcl Interface Guide Version J- December Comments E- mail your comments about this manual to leda-support synopsys com CCopyright Notice and Proprietary Information Copyright ? Synopsys Inc All rights reserved This software and documentation contain con ?dential and proprietary information that is the property of Synopsys Inc The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement No part of the software and documentation may be reproduced transmitted or translated in any form or by any means electronic mechanical manual optical or otherwise without prior written permission of Synopsys Inc or as expressly provided by the license agreement Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America Disclosure to nationals of other countries contrary to United States law is prohibited It is the reader ? s responsibility to determine the applicable regulations and to comply with them Disclaimer SYNOPSYS INC AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Registered Trademarks Synopsys AMPS Arcadia C Level Design C HDL C V C VHDL Cadabra Calaveras Algorithm CATS CSim Design Compiler DesignPower DesignWare EPIC Formality HSPICE Hypermodel iN-Phase in-Sync Leda MAST Meta Meta- Software ModelAccess ModelTools NanoSim OpenVera PathMill Photolynx Physical Compiler PowerMill PrimeTime RailMill Raphael RapidScript Saber SiVL SNUG SolvNet Stream Driven Simulator Superlog System Compiler Testify TetraMAX TimeMill TMA VCS Vera and Virtual Stepper are registered trademarks of Synopsys Inc Trademarks abraCAD abraMAP Active Parasitics AFGen Apollo Apollo II Apollo- DPII Apollo-GA ApolloGAII Astro Astro-Rail Astro-Xtalk Aurora AvanTestchip AvanWaves BCView Behavioral Compiler BOA BRT Cedar ChipPlanner Circuit Analysis Columbia Columbia-CE Comet D Cosmos CosmosEnterprise CosmosLE CosmosScope CosmosSE Cyclelink Davinci DC Expert DC Expert Plus DC Professional DC Ultra DC Ultra Plus Design Advisor Design Analyzer Design Vision DesignerHDL DesignTime DFM- Workbench DFT Compiler Direct RTL Direct Silicon Access Discovery DW DWPCI Dynamic-Macromodeling Dynamic Model Switcher ECL Compiler ECO Compiler EDAnavigator Encore Encore PQ Evaccess ExpressModel Floorplan Manager Formal Model Checker FoundryModel FPGA Compiler II FPGA Express Frame Compiler Galaxy Gatran HDL Advisor HDL Compiler Hercules Hercules-Explorer Hercules-II Hierarchical Optimization Technology High Performance Option HotPlace HSPICE-Link iN-Tandem Integrator Interactive Waveform Viewer i-Virtual Stepper Jupiter Jupiter-DP JupiterXT JupiterXT-ASIC JVXtreme Liberty Libra-Passport Library Compiler Libra-Visa Magellan Mars Mars-Rail MarsXtalk Medici Metacapture Metacircuit Metamanager Metamixsim Milkyway ModelSource Module Compiler MS MS - Nova Product Family Nova-ExploreRTL Nova-Trans Nova-VeriLint Nova-VHDLlint Optimum Silicon Orion ec Parasitic View Passport Planet Planet-PL Planet-RTL Polaris Polaris-CBS Polaris-MT Power Compiler PowerCODE PowerGate ProFPGA ProGen Prospector Protocol Compiler PSMGen Raphael-NES RoadRunner RTL Analyzer Saturn ScanBand Schematic Compiler Scirocco Scirocco-i Shadow Debugger Silicon Blueprint Silicon Early Access SinglePass-SoC Smart Extraction SmartLicense SmartModel Library Softwire Source-Level Design Star Star-DC Star-MS Star-MTB Star-Power Star-Rail Star-RC Star-RCXT Star-Sim StarSimXT Star-Time Star-XP SWIFT Taurus Taurus-Device Taurus-Layout Taurus-Lithography Taurus-Process Taurus-Topography Taurus-Visual