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Victor H. Kee, BASc, P.Eng http://www.ultratech-labs.com vic@ultratech-labs.com

Victor H. Kee, BASc, P.Eng http://www.ultratech-labs.com vic@ultratech-labs.com Phone: (905) 829-1570 Fax: (905) 829-8050 EMC Design Guide Issue 4, Sep 2013 ©Ultratech Group of Labs 2013 (All rights reserved) Page i EMC Product Design Guide Prepared by: Victor H. Kee, P.Eng VP Marketing & Business Development Ultratech Group of labs 3000 Bristol Circle Oakville, Ontario Canada. L6H 6G4 Phone: (905) 829-1570 Fax: (905) 829-8050 Victor H. Kee, BASc, P.Eng http://www.ultratech-labs.com vic@ultratech-labs.com Phone: (905) 829-1570 Fax: (905) 829-8050 EMC Design Guide Issue 4, Sep 2013 ©Ultratech Group of Labs 2013 (All rights reserved) Page ii Table of Contents EMC COMPLIANCE BY DESIGN .................................................................................................................... 1 The Cost of Non-Compliance .......................................................................................................................... 2 THE PCB (PRINTED CIRCUIT BOARD) ..................................................................................................... 3 Single or Multilayer ..................................................................................................................................... 3 Choosing the right logic family ................................................................................................................... 3 The Current Loop ......................................................................................................................................... 5 Reducing Current Loops .............................................................................................................................. 5 Spread-spectrum clocking (SST CLK) ........................................................................................................ 7 Power Grids ................................................................................................................................................. 8 De-coupling Capacitor Values ..................................................................................................................... 9 Matching the high speed clock lines .......................................................................................................... 10 Isolating PCB Areas ................................................................................................................................... 12 Interface and Connector Ports .................................................................................................................... 13 Component Placement and Layout on the PCB ......................................................................................... 15 PCB Plane Topography and edge effects ................................................................................................... 16 The PCB area under I/O Connectors ......................................................................................................... 17 Filter Bypass .............................................................................................................................................. 18 Operational amplifers, comparators and buffers ........................................................................................ 19 Hardening Reset lines ................................................................................................................................ 20 ESD Countermeasures ............................................................................................................................... 20 Watch Dog Timers ..................................................................................................................................... 21 Transient Protection ................................................................................................................................... 21 The Power Supply .......................................................................................................................................... 22 Filtering of AC power line ......................................................................................................................... 22 Suppressing ground loops .......................................................................................................................... 24 Switch Mode Device Transients ................................................................................................................ 25 Transformer concerns ................................................................................................................................ 25 Snubbers on Output Diodes ....................................................................................................................... 26 DC output Common-mode Filter ............................................................................................................... 26 I/O Cables and Connectors ............................................................................................................................ 27 Internal Cables ........................................................................................................................................... 28 The Ethernet Port ....................................................................................................................................... 28 The Chassis Enclosure ................................................................................................................................... 30 Grounding ...................................................................................................................................................... 31 Preparing a sample for EMC tests ................................................................................................................. 33 FINDING A COST-EFFECTIVE SOLUTION TO NON-COMPLIANCE ................................................. 35 PCB Layout ................................................................................................................................................ 35 Cable, Cables, Cables.... ............................................................................................................................ 35 Chassis Construction .................................................................................................................................. 36 EMC Design Guide Summary ....................................................................................................................... 37 Victor H. Kee, BASc, P.Eng http://www.ultratech-labs.com vic@ultratech-labs.com Phone: (905) 829-1570 Fax: (905) 829-8050 EMC Design Guide Issue 4, Sep 2013 ©Ultratech Group of Labs 2013 (All rights reserved) Page 1 EMC COMPLIANCE BY DESIGN EMC compliance can be approached in several ways. The most common approach taken is to design the product for functionality and price and then to test the product to obtain final product certification prior to the marketing of the product. This approach is still the most common used and often results in band-aid and add- on fixes at the production stage to resolve emissions and immunity problems not taken into account in the initial product procurement specifications. In the majority of situations, a product stands ready to ship pending the final acquisition of the product certifications. The time spent in bringing a product into compliance after it has been designed and prototyped usually impacts the whole sales and marketing process and in some special cases, has been known to put a company under. Our most often made request when this happens is: "Bring the product into compliance without making any changes!!!" Sadly enough, we live in the real world of cause and effect and once the product has been finalized for production, the noise suppression options available to us reduces substantially and even these can be quite costly to implement in mass production runs. Statistically speaking, about 80% of the products we test for compliance need some degree of added suppression for emissions and/or immunity. Since the subject of noise suppression is not taught formally in most universities and colleges, most design engineers will have to go through the school of "hard knocks" to acquire the experience and training in order to produce regulatory compliant designs. The design team can only do this through a coordinated effort involving both the mechanical and electrical departments since noise suppression is often three dimensional in nature. The best approach to compliance design is to be able to anticipate at each design stage, potential noise issues and to suppress them early in the design cycle. This is by far the best and most cost-effective approach and is one we highly recommend. Noise suppression in this way, can be taken one step at a time rather than waiting until the product is ready for production. Once this strategy has been adopted, the noise mitigation techniques will often be simple and straightforward to implement because there are less constraints on the techniques available. Over design is part of an engineering trait used to provide a safety margin to take into account deviations of tolerances in components and processes. Bulletproofing a design from the viewpoint of noise suppression can only enhance the performance of the product especially in processing analog signals such as audio and video signals. Experience has shown that designs, which incorporate suppression at each design stage, have a 90% chance of meeting the final requirements without the need of additional suppression with the added benefit of improved signal integrity. Victor H. Kee, BASc, P.Eng http://www.ultratech-labs.com vic@ultratech-labs.com Phone: (905) 829-1570 Fax: (905) 829-8050 EMC Design Guide Issue 4, Sep 2013 ©Ultratech Group of Labs 2013 (All rights reserved) Page 2 THE COST OF NON-COMPLIANCE The average cost of compliance increases on an exponential curve with respect to product development cycle. If taken into account in the early stages of product development, the costs are minimal. If left to the production or field retrofit stage, the costs can be exponential in nature and extremely prohibitive to implement. Figure 1 Exponential cost of mitigation Cost of compliance Product Development Cycle Design Prototype & Pre-production Production Field Retrofit The Average Cost of Product Compliance Victor H. Kee, BASc, P.Eng http://www.ultratech-labs.com vic@ultratech-labs.com Phone: (905) 829-1570 Fax: (905) 829-8050 EMC Design Guide Issue 4, Sep 2013 ©Ultratech Group of Labs 2013 (All rights reserved) Page 3 THE PCB (PRINTED CIRCUIT BOARD) The PCB is the primary originator of noise. As such the layout and structure of the PCB should be treated with paramount importance to noise suppression. It has been shown that the major contributing source to noise occurring on PCB structures is the common mode noise component and not the differential mode component. Figure 2 Common mode concepts Single or Multilayer The first step in PCB suppression is deciding on the PCB structure itself. i.e. single layer double sided, over a multi-layered board with embedded ground and power supply planes. EMC test engineers will tell you that multi-layered boards are quieter than equivalently laid out single layered boards. The degree of suppression offered by using a multi-layered board varies from anywhere from 8 to 15dB depending on the density of the board. The major drawback of going multilayer is the cost, which is usually more than double that of a single layered board. Obviously there is a trade off between cost and noise reduction. The choice of how many layers to use has often depended on the density and complexity of the circuit. Seldom has the high frequency content of a circuit entered into the decision of choosing the type of PCB to use. Even a simple circuit, which possesses many oscillator components, warrants consideration for going with a multi-layer design. This is not to say that a single layered board will not comply with the emissions or immunity requirements. Careful attention to layout and parts placement will often aid a design in meeting all the emissions and immunity requirements. Choosing the right logic family The basic rule of thumb is use the lowest speed logic family that your application requires - especially in critical areas such as buffers and drivers on data and memory buses. The fast rise times of high speed logic give rise to large overshoots and ringing which translate into high frequency content in the ensuing spectra. Victor H. Kee, BASc, P.Eng http://www.ultratech-labs.com vic@ultratech-labs.com Phone: (905) 829-1570 Fax: (905) 829-8050 EMC Design Guide Issue 4, Sep 2013 ©Ultratech Group of Labs 2013 (All rights reserved) Page 4 The characteristics of the most common logic families are provided as follows: Logic Family Frequency Limit (MHz) Typical Rise-time (ns) Typical Fall-time (ns) Typical Slew rate (V/ns) 74 25 10.6 4.36 0.68 74LS 33 8.67 4.45 0.67 74ALS 35 7.27 7.27 0.85 74HCT 50 3.29 3.29 1.15 74S 95 5.0 3.05 0.98 74AS 125 3.9 3.28 0.9 74F 125 4.0 3.01 1.0 74G 1125 0.8 0.8 ECLinPS 1,200 0.6 0.3 0.85 GaAS 15,000 0.04 0.03 0.075 *above data taken on a 10MHz clock signal The above selection should be kept in mind when trouble shooting emissions problems as moving to a slower speed logic family on a critical IC can buy as much as 5dB in terms of noise suppression. This is especially true of buffers and bus driver chips since bus sizes of 16, 24 and 32 bit are not uncommon and the wider the bus, the more critical will be the choice of logic family. Often moving to a slower driver chip can result in a significant improvement in overall emissions characteristics without having to re-spin a PCB layout. Figure uploads/Industriel/ design-guide-2013.pdf