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Programming with Bluespec SystemVerilog: Design Methodologies, Styles, Patterns

Programming with Bluespec SystemVerilog: Design Methodologies, Styles, Patterns and Examples Preliminary Draft Please do not circulate without permission from Bluespec, Inc. Revision: 24 November 2008 Copyright c ⃝2000 – 2008 Bluespec, Inc. This document describes Bluespec SystemVerilog coding guidelines though a series of descriptions and examples, where the objectives are to: • bring experienced Verilog and VHDL designers up to speed with the abilities and features of Bluespec, • produce expected RTL with respect to interfaces, and structures, • take advantage of the extensive libraries provided by Bluespec. This document is organized into several sections which need not be read in sequence. Rather, each section gives hints, advice and examples on particular design or programming structures. This document is not intended to replace the Reference Guide or the User’s guide. It is a intended only as a supplement to aid designers in expressing their designs in the Bluespec environment. This document is under development. 1 Contents Table of Contents 2 1 Types 4 1.1 Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Non Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 Conversion Between Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 Types from the Bluespec Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Designing Interfaces 8 2.1 Interface Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Sharing Signals in an Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Combining Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 Basic Interfaces from the Bluespec Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 Interface Paradigms from the Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Logic Representation 12 3.1 Sequential Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Combinational Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 System Design Examples 13 4.1 Synchronous State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 Deﬁning Interface Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 Extracting pieces from an interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4 Using RWire to Avoid Registers and Latency . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 Testbenches 18 5.1 Controlling Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 Stored Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3 Generating Random Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 Common Hints and Style Suggestions 21 6.1 Identiﬁer Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 Use let Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 Using types instead of ‘deﬁnes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.4 Adding Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2 7 Helping the Scheduler 23 7.1 Rules versus Always Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2 Alleviating Read/Write Conﬂicts with ConﬁgReg . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3 Register Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 Debugging Hints and Tips 26 8.1 Viewing Complex Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9 BlueSim 29 9.1 Improving Simulation Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10 Other Notes 30 10.1 Using Bluespec with other tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11 Using Existing Verilog Components in a BSV Design 31 11.1 Sample Verilog Memory Import . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3 1 Types Bluespec provides a strong, static type-checking environment. Everything has a type; that is, every variable and every expression has a type. Variables must be assigned values which have compatible types. Type checking, which occurs before program elaboration or execution, ensures that object types are compatible and that needed conversion functions are valid for the context. This section describes common types and structures as deﬁned and used in uploads/Litterature/ programming-with-bluespec-systemverilog-design-methodologies-styles-patterns-and-examples.pdf