Remerciez-le!

Remerciez @Admin pour avoir partagé cet document gratuitement, de la manière la plus simple, en partageant sur les réseaux sociaux.

Constraints Guide — ISE 5 Printed in U.S.A. Constraints Guide Constraints Guide

Constraints Guide — ISE 5 Printed in U.S.A. Constraints Guide Constraints Guide ii Xilinx Development System “Xilinx” and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved. CoolRunner, RocketChips, RocketIP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are registered trademarks of Xilinx, Inc. The shadow X shown above is a trademark of Xilinx, Inc. ACE Controller, ACE Flash, A.K.A. Speed, Alliance Series, AllianceCORE, Bencher, ChipScope, Configurable Logic Cell, CORE Generator, CoreLINX, Dual Block, EZTag, Fast CLK, Fast CONNECT, Fast FLASH, FastMap, Fast Zero Power, Foundation, Gigabit Speeds...and Beyond!, HardWire, HDL Bencher, IRL, J Drive, JBits, LCA, LogiBLOX, Logic Cell, LogiCORE, LogicProfessor, MicroBlaze, MicroVia, MultiLINX, NanoBlaze, PicoBlaze, PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI, Rocket I/O, SelectI/O, SelectRAM, SelectRAM+, Silicon Xpresso, Smartguide, Smart-IP, SmartSearch, SMARTswitch, System ACE, Testbench In A Minute, TrueMap, UIM, VectorMaze, VersaBlock, VersaRing, Virtex-II Pro, Virtex-II EasyPath, Wave Table, WebFITTER, WebPACK, WebPOWERED, XABEL, XACT-Floorplanner, XACT-Performance, XACTstep Advanced, XACTstep Foundry, XAM, XAPP, X-BLOX +, XC designated products, XChecker, XDM, XEPLD, Xilinx Foundation Series, Xilinx XDTV, Xinfo, XSI, XtremeDSP, and ZERO+ are trademarks of Xilinx, Inc. The Programmable Logic Company is a service mark of Xilinx, Inc. All other trademarks are the property of their respective owners. Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx, Inc. reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible. Xilinx, Inc. will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx provides any design, code, or information shown or described herein "as is." By providing the design, code, or information as one possible implementation of a feature, application, or standard, Xilinx makes no representation that such implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation, including but not limited to any warranties or representations that the implementation is free from claims of infringement, as well as any implied warranties of merchantability or fitness for a particular purpose. Xilinx, Inc. devices and products are protected under U.S. Patents. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein are free from patent infringement or from any other third party right. Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user. Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited. The contents of this manual are owned and copyrighted by Xilinx. © Copyright 1994-2002 Xilinx, Inc. All Rights Reserved. Except as stated herein, none of the material may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of Xilinx. Any unauthorized use of any material contained in this manual may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statues. R Constraints Guide iii About This Manual This chapter contains the following sections: • “Manual Contents” • “Additional Resources” Manual Contents This book contains the following chapters. • “Introduction” • “Constraint Types” • “Constraint Entry” • “Third-Party Constraints” • “Timing Constraint Strategies” • Chapters organized alphabetically containing information on individual constraints. For a list of the constraints, see the “Constraints Chart” appendix. Constraints Guide iv Xilinx Development System Additional Resources For additional information, go to http://support.xilinx.com. The following table lists some of the resources on this Web site. Resource Description/URL Tutorials Tutorials covering Xilinx design flows, from design entry to verification and debugging http://support.xilinx.com/support/techsup/tutorials/index.htm Answers Database Current listing of solution records for the Xilinx software tools Search this database using the search function at http://support.xilinx.com/support/searchtd.htm Application Notes Descriptions of device-specific design techniques and approaches http://support.xilinx.com/apps/appsweb.htm Data Book Pages from The Programmable Logic Data Book, which contains device- specific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging http://support.xilinx.com/partinfo/databook.htm Xcell Journals Quarterly journals for Xilinx programmable logic users http://support.xilinx.com/xcell/xcell.htm Technical Tips Latest news, design tips, and patch information for the Xilinx design environment http://support.xilinx.com/support/techsup/journals/index.htm Conventions Constraints Guide v Conventions This manual uses the following conventions. An example illustrates most conventions. Typographical The following conventions are used for all documents. • Courier font indicates messages, prompts, and program files that the system displays. speed grade: - 100 • Courier bold indicates literal commands that you enter in a syntactical statement. However, braces “{ }” in Courier bold are not literal and square brackets “[ ]” in Courier bold are literal only in the case of bus specifications, such as bus [7:0]. rpt_del_net= Courier bold also indicates commands that you select from a menu. File → Open • Italic font denotes the following items. ♦ Variables in a syntax statement for which you must supply values edif2ngd design_name ♦ References to other manuals See the Development System Reference Guide for more information. Constraints Guide vi Xilinx Development System ♦ Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected. • Square brackets “[ ]” indicate an optional entry or parameter. However, in bus specifications, such as bus [7:0], they are required. edif2ngd [option_name] design_name • Braces “{ }” enclose a list of items from which you must choose one or more. lowpwr ={on|off} • A vertical bar “|” separates items in a list of choices. lowpwr ={on|off} • A vertical ellipsis indicates repetitive material that has been omitted. IOB #1: Name = QOUT’ IOB #2: Name = CLKIN’ . . . • A horizontal ellipsis “…” indicates that an item can be repeated one or more times. allow block block_name loc1 loc2 … locn; Online Document The following conventions are used for online documents. • Blue text indicates cross-references within a book. Red text indicates cross-references to other books. Click the colored text to jump to the specified cross-reference. • Blue, underlined text indicates a Web site. Click the link to open the specified Web site. You must have a Web browser and internet connection to use this feature. Constraints Guide vii Contents About This Manual Manual Contents ...........................................................................iii Additional Resources ....................................................................iv Conventions Typographical ................................................................................v Online Document ..........................................................................vi Chapter 1 Introduction Manual Description .......................................................................1-1 Architecture Support .....................................................................1-2 Chapter 2 Constraint Types Timing Constraints ........................................................................2-1 XST Timing Constraints ...........................................................2-2 Global Timing Constraints Support ..........................................2-4 Domain Definitions ...................................................................2-5 XCF Timing Constraint Support ...............................................2-6 Old Timing Constraint Support .................................................2-8 Timing Model ...........................................................................2-12 Priority ......................................................................................2-12 Limitations ................................................................................2-12 List of Timing and Grouping Constraints ..................................2-12 Placement Constraints ..................................................................2-14 Relative Location (RLOC) Constraints .....................................2-15 Relationally Placed Macros (RPMs) ........................................2-15 Grouping Constraints ....................................................................2-17 Using Predefined Groups .........................................................2-18 Predefined Group Examples ....................................................2-18 BRAMS_PORTA and BRAMS_PORTB Examples ..................2-19 Mapping Directives ........................................................................2-20 Routing Directives .........................................................................2-22 Modular Design Constraints ..........................................................2-23 Overview ..................................................................................2-23 List of Modular Design Constraints ..........................................2-23 Constraints Guide viii Xilinx Development System Synthesis Constraints ...................................................................2-24 CPLD Fitter ...................................................................................2-27 Initialization Directives ...................................................................2-28 DLL/DCM Constraints ...................................................................2-29 Logical and Physical Constraints ..................................................2-30 Logical Constraints ..................................................................2-30 Physical Constraints ................................................................2-31 Attributes .......................................................................................2-31 Chapter 3 Constraint Entry ECS Schematic Designs ...............................................................3-2 VHDL .............................................................................................3-3 Verilog ...........................................................................................3-4 ABEL .............................................................................................3-4 NCF ...............................................................................................3-4 UCF ...............................................................................................3-5 UCF Flow .................................................................................3-5 Manual Entry of Timing Constraints .........................................3-6 UCF/NCF File Syntax ..............................................................3-6 General Rules .....................................................................3-7 Conflict in Constraints .........................................................3-8 Syntax .................................................................................3-8 Specifying Attributes for TIMEGRP and TIMESPEC ..........3-8 Using Reserved Words .......................................................3-9 Wildcards ............................................................................3-9 Traversing Hierarchies ........................................................3-10 Entering Multiple Constraints ..............................................3-11 File Name ...........................................................................3-11 Instances and Blocks ..........................................................3-12 Constraints Editor ..........................................................................3-13 Input/Output Files .....................................................................3-13 Starting the Constraints Editor .................................................3-14 From the Project Navigator .................................................3-14 As a Standalone .................................................................3-14 From the Command Line ....................................................3-14 Obtaining Online Help ..............................................................3-15 Exiting the Constraints Editor ...................................................3-15 UCF Syntax ..............................................................................3-16 Group Elements Associated by Nets (TNM_Net) ...............3-16 Group Elements by Instance Name (TNM) .........................3-16 Group Elements by Element Output Net Name Schematic Users (TIMEGRP) .............................................3-17 Timing THRU Points (TPTHRU) .........................................3-17 Pad to Setup .......................................................................3-17 Clock to Pad .......................................................................3-18 Slow/Fast Path Exceptions (FROM TO) .............................3-19 Multicycle Paths (FROM/THRU/TO) ...................................3-19 False Paths (FROM TO TIG) ..............................................3-19 False Paths by Net (Net TIG) .............................................3-20 Contents Constraints Guide ix Period .................................................................................3-20 Location ..............................................................................3-21 Prohibit I/O Locations .........................................................3-21 FAST/SLOW .......................................................................3-21 PULLUP/PULLDOWN ........................................................3-21 DRIVE .................................................................................3-22 IOSTANDARD (Virtex devices only) ...................................3-22 VOLTAGE ...........................................................................3-23 TEMPERATURE .................................................................3-23 PCF Files ......................................................................................3-23 Constraint Files for XST ................................................................3-26 XCF ..........................................................................................3-26 XCF Specification ...............................................................3-26 XCF Syntax and Utilization .................................................3-27 Old XST Constraint File ...........................................................3-29 uploads/Voyage/ constraints-guide.pdf