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Guide lvs Guide to Passing LVS Layout vs Schematic A Cadence Help Document Document Contents Introduction Golden Rules Understanding the LVS Output File Example LVS Output File Solutions to Common LVS Problems Tools and Techniques for Passing LVS Introduc

Guide to Passing LVS Layout vs Schematic A Cadence Help Document Document Contents Introduction Golden Rules Understanding the LVS Output File Example LVS Output File Solutions to Common LVS Problems Tools and Techniques for Passing LVS Introduction Cadence Tutorial B describes the steps for running an LVS Layout vs Schematic comparison to verify the layout and schematic for a cell exactly match This document describes techniques for tracking down and ?xing problems that cause LVS to fail or not pass Passing LVS for a circuit is critical to ensure the physical design will perform as intended when the circuit is fabricated However passing LVS can be one of the most di ?cult and time consuming tasks of the design ow because often the problems are hard to track down The Cadence LVS tool provides several sources of information which can be used to ?nd and debug the problems that caused LVS to fail or not pass This document brie y describes some of these information sources and provides some techniques for solving common LVS problems Golden Rules ? Always verify the operation of a circuit via simulations at the schematic level before attempting to layout the cell LVS only veri ?es the schematic and layout match so if the schematic does not work the layout will not either If the schematic does not function properly there is no reason to spend time debugging the LVS ? Always design in a hierarchical fashion building smaller lower level cells before constructing larger circuit blocks from the lower level cells ? Always pass LVS on lower level cells before attempting to check LVS on a higher- level cell If the lower level cells do not pass LVS it is much easier to debug them on their own than after you have added the cell to a higher level circuit ? Always re-check LVS on a cell if you make any changes to the schematic or layout ? If you modify a layout to correct a problem found in an LVS check always re-extract the layout and save it before running the LVS checker again Understanding the LVS Output File The LVS Output File provides a lot of useful information about a cell including the number of devices nets etc within the cell It also lists some results that can be useful in tracking down errors that caused LVS not to pass An example LVS Output File for a cell that has passed LVS is given below The ?ve color-coded and numbered subsections of the LVS output ?le are The Netlist summary for the layout and the schematic Guide to Passing LVS C ? This is a very important indicator of problems If the netlists match as they do above you will notice that the numbers for the Nets Terminals NMOS and PMOS all match A quick description of these o NETS ?? These are the wires or connections in a device In your inverter the output which connects the drain of you PMOS