Remerciez-le!

Remerciez @Admin pour avoir partagé cet document gratuitement, de la manière la plus simple, en partageant sur les réseaux sociaux.

Cshin 001 042 Advanced MOSFET Designs and Implications for SRAM Scaling By Changhwan Shin A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering - Electrical Engineering and Computer Scie

Advanced MOSFET Designs and Implications for SRAM Scaling By Changhwan Shin A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences in the Graduate Division of the University of California Berkeley Committee in charge Professor Tsu-Jae King Liu Chair Professor Borivoje Nikoli ? Professor Eugene E Haller Spring CAdvanced MOSFET Designs and Implications for SRAM Scaling Copyright ? by Changhwan Shin CAbstract Advanced MOSFET Designs and Implications for SRAM Scaling by Changhwan Shin Doctor of Philosophy in Engineering ?? Electrical Engineering and Computer Sciences University of California Berkeley Professor Tsu-Jae King Liu Chair Continued planar bulk MOSFET scaling is becoming increasingly di ?cult due to increased random variation in transistor performance with decreasing gate length and thereby scaling of SRAM using minimum-size transistors is further challenging This dissertation will discuss various advanced MOSFET designs and their bene ?ts for extending density and voltage scaling of static memory SRAM arrays Using threedimensional -D process and design simulations transistor designs are optimized Then using an analytical compact model calibrated to the simulated transistor current-vs -voltage characteristics the performance and yield of six-transistor -T SRAM cells are estimated For a given cell area fully depleted silicon-on-insulator FD-SOI MOSFET technology is projected to provide for signi ?cantly improved yield across a wide range of operating voltages as compared with conventional planar bulk CMOS technology Quasi-Planar QP bulk silicon MOSFETs are a lower-cost alternative and also can provide for improved SRAM yield A more printable notchless QP bulk SRAM cell layout is proposed to reduce lithographic variations and is projected to achieve six-sigma yield required for terabit- scale SRAM arrays with a minimum operating voltage below Volt Professor Tsu-Jae King Liu Chair Dissertation Committee Chair CTo my parents for their unbounded love and support to my brother for his sincere encouragement and to my wife for her devoted love i CContents Table of Contents ii List of Figures viii List of Tables x Acknowledgements xi Table of Contents Chapter Introduction ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Static Random Access Memory SRAM ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SRAM Basics ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Alternative SRAM Cell Architectures ? ? ? ? ? ? ? ? ? ? ? ? ? ? Sources of VT Variation ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Random Dopant Fluctuations RDF ? ? ? ? ? ? ? ? ? ? ? Gate Length Fluctuations ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Gate Work-Function Variation WFV ? ? ? ? ? ? ? ? ? ? Approaches to Mitigating the Impact of VT Variation for SRAM