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TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide Literature Number:

TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide Literature Number: SPRU732J July 2010 2 SPRU732J–July 2010 Copyright © 2010, Texas Instruments Incorporated Contents Preface ...................................................................................................................................... 15 1 Introduction ...................................................................................................................... 17 1.1 TMS320 DSP Family Overview .......................................................................................... 18 1.2 TMS320C6000 DSP Family Overview .................................................................................. 18 1.3 TMS320C64x DSP Features and Options ............................................................................. 20 1.4 TMS320C64x/C64x+ DSP Architecture ................................................................................ 21 1.4.1 Central Processing Unit (CPU) ................................................................................. 23 1.4.2 Internal Memory .................................................................................................. 23 1.4.3 Memory and Peripheral Options ................................................................................ 23 2 CPU Data Paths and Control ............................................................................................... 25 2.1 Introduction ................................................................................................................. 26 2.2 General-Purpose Register Files ......................................................................................... 26 2.3 Functional Units ............................................................................................................ 29 2.4 Register File Cross Paths ................................................................................................ 30 2.5 Memory, Load, and Store Paths ......................................................................................... 31 2.6 Data Address Paths ....................................................................................................... 31 2.7 Galois Field ................................................................................................................. 31 2.7.1 Special Timing Considerations ................................................................................. 33 2.8 Control Register File ...................................................................................................... 34 2.8.1 Register Addresses for Accessing the Control Registers ................................................... 35 2.8.2 Pipeline/Timing of Control Register Accesses ................................................................ 35 2.8.3 Addressing Mode Register (AMR) ............................................................................. 36 2.8.4 Control Status Register (CSR) .................................................................................. 38 2.8.5 Galois Field Polynomial Generator Function Register (GFPGFR) ......................................... 40 2.8.6 Interrupt Clear Register (ICR) ................................................................................... 41 2.8.7 Interrupt Enable Register (IER) ................................................................................. 42 2.8.8 Interrupt Flag Register (IFR) .................................................................................... 43 2.8.9 Interrupt Return Pointer Register (IRP) ........................................................................ 43 2.8.10 Interrupt Set Register (ISR) .................................................................................... 44 2.8.11 Interrupt Service Table Pointer Register (ISTP) ............................................................. 45 2.8.12 Nonmaskable Interrupt (NMI) Return Pointer Register (NRP) ............................................. 45 2.8.13 E1 Phase Program Counter (PCE1) .......................................................................... 46 2.9 Control Register File Extensions ........................................................................................ 46 2.9.1 Debug Interrupt Enable Register (DIER) ...................................................................... 47 2.9.2 DSP Core Number Register (DNUM) .......................................................................... 48 2.9.3 Exception Clear Register (ECR) ................................................................................ 48 2.9.4 Exception Flag Register (EFR) ................................................................................. 49 2.9.5 GMPY Polynomial—A Side Register (GPLYA) ............................................................... 50 2.9.6 GMPY Polynomial—B Side Register (GPLYB) ............................................................... 50 2.9.7 Internal Exception Report Register (IERR) ................................................................... 51 2.9.8 SPLOOP Inner Loop Count Register (ILC) ................................................................... 52 2.9.9 Interrupt Task State Register (ITSR) ........................................................................... 52 2.9.10 NMI/Exception Task State Register (NTSR) ................................................................. 53 2.9.11 Restricted Entry Point Register (REP) ........................................................................ 53 2.9.12 SPLOOP Reload Inner Loop Count Register (RILC) ....................................................... 54 3 SPRU732J–July 2010 Contents Copyright © 2010, Texas Instruments Incorporated www.ti.com 2.9.13 Saturation Status Register (SSR) ............................................................................. 54 2.9.14 Time Stamp Counter Registers (TSCL and TSCH) ......................................................... 55 2.9.15 Task State Register (TSR) ..................................................................................... 57 3 Instruction Set .................................................................................................................. 59 3.1 Instruction Operation and Execution Notations ........................................................................ 60 3.2 Instruction Syntax and Opcode Notations .............................................................................. 62 3.2.1 32-Bit Opcode Maps ............................................................................................. 63 3.2.2 16-Bit Opcode Maps ............................................................................................. 63 3.3 Delay Slots ................................................................................................................. 64 3.4 Parallel Operations ........................................................................................................ 65 3.4.1 Example Parallel Code .......................................................................................... 67 3.4.2 Branching Into the Middle of an Execute Packet ............................................................. 67 3.5 Conditional Operations ................................................................................................... 68 3.6 SPMASKed Operations ................................................................................................... 68 3.7 Resource Constraints ..................................................................................................... 69 3.7.1 Constraints on Instructions Using the Same Functional Unit ............................................... 69 3.7.2 Constraints on the Same Functional Unit Writing in the Same Instruction Cycle ........................ 69 3.7.3 Constraints on Cross Paths (1X and 2X) ...................................................................... 69 3.7.4 Cross Path Stalls ................................................................................................. 70 3.7.5 Constraints on Loads and Stores .............................................................................. 71 3.7.6 Constraints on Long (40-Bit) Data .............................................................................. 71 3.7.7 Constraints on Register Reads ................................................................................. 72 3.7.8 Constraints on Register Writes ................................................................................. 72 3.7.9 Constraints on AMR Writes ..................................................................................... 73 3.7.10 Constraints on Multicycle NOPs ............................................................................... 73 3.7.11 Constraints on Unitless Instructions .......................................................................... 73 3.8 Addressing Modes ......................................................................................................... 76 3.8.1 Linear Addressing Mode ......................................................................................... 76 3.8.2 Circular Addressing Mode ....................................................................................... 77 3.8.3 Syntax for Load/Store Address Generation ................................................................... 79 3.9 Compact Instructions on the C64x+ CPU .............................................................................. 80 3.9.1 Compact Instruction Overview .................................................................................. 80 3.9.2 Header Word Format ............................................................................................. 81 3.9.3 Processing of Fetch Packets .................................................................................... 85 3.9.4 Execute Packet Restrictions .................................................................................... 85 3.9.5 Available Compact Instructions ................................................................................. 85 3.10 Instruction Compatibility .................................................................................................. 86 3.11 Instruction Descriptions ................................................................................................... 87 4 Pipeline .......................................................................................................................... 509 4.1 Pipeline Operation Overview ........................................................................................... 510 4.1.1 Fetch .............................................................................................................. 511 4.1.2 Decode ........................................................................................................... 512 4.1.3 Execute ........................................................................................................... 513 4.1.4 Pipeline Operation Summary .................................................................................. 514 4.2 Pipeline Execution of Instruction Types ............................................................................... 518 4.2.1 Single-Cycle Instructions ....................................................................................... 519 4.2.2 Two-Cycle Instructions and .M Unit Nonmultiply Operations ............................................. 520 4.2.3 Store Instructions ............................................................................................... 521 4.2.4 Extended Multiply Instructions ................................................................................. 523 4.2.5 Load Instructions ................................................................................................ 524 4.2.6 Branch Instructions ............................................................................................. 525 4.3 Performance Considerations ........................................................................................... 527 4.3.1 Pipeline Operation With Multiple Execute Packets in a Fetch Packet ................................... 527 4 Contents SPRU732J–July 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com 4.3.2 Multicycle NOPs ................................................................................................. 529 4.3.3 Memory Considerations ........................................................................................ 530 4.4 C64x+ DSP Differences ................................................................................................. 531 5 Interrupts ........................................................................................................................ 533 5.1 Overview .................................................................................................................. 534 5.1.1 Types of Interrupts and Signals Used ........................................................................ 534 5.1.2 Interrupt Service Table (IST) .................................................................................. 536 5.1.3 Summary of Interrupt Control Registers ..................................................................... 540 5.2 Globally Enabling and Disabling Interrupts ........................................................................... 540 5.3 Individual Interrupt Control .............................................................................................. 543 5.3.1 Enabling and Disabling Interrupts ............................................................................. 543 5.3.2 Status of Interrupts .............................................................................................. 543 5.3.3 Setting and Clearing Interrupts ................................................................................ 544 5.3.4 Returning From Interrupt Servicing ........................................................................... 544 5.4 Interrupt Detection and Processing on the C64x CPU .............................................................. 545 5.4.1 Setting the Nonreset Interrupt Flag ........................................................................... 545 5.4.2 Conditions for Processing a Nonreset Interrupt ............................................................. 546 5.4.3 Actions Taken During Nonreset Interrupt Processing ...................................................... 547 5.4.4 Setting the RESET Interrupt Flag ............................................................................. 547 5.4.5 Actions Taken During RESET Interrupt Processing ........................................................ 548 5.5 Interrupt Detection and Processing on the C64x+ CPU ............................................................ 548 5.5.1 Setting the Nonreset Interrupt Flag ........................................................................... 548 5.5.2 Conditions for Processing a Nonreset Interrupt ............................................................. 549 5.5.3 Saving TSR Context in Nonreset Interrupt Processing .................................................... 551 5.5.4 Actions Taken During Nonreset Interrupt Processing ...................................................... 552 5.5.5 Conditions for Processing a Nonmaskable Interrupt ....................................................... 552 5.5.6 Saving of Context in Nonmaskable Interrupt Processing .................................................. 555 5.5.7 Actions Taken During Nonmaskable Interrupt Processing ................................................ 555 5.5.8 Setting the RESET Interrupt Flag ............................................................................. 555 5.5.9 Actions Taken During RESET Interrupt Processing ........................................................ 556 5.6 Performance Considerations ........................................................................................... 557 5.6.1 General Performance ........................................................................................... 557 5.6.2 Pipeline Interaction ............................................................................................. 557 5.7 Programming Considerations .......................................................................................... 557 5.7.1 Single Assignment Programming ............................................................................. 557 5.7.2 Nested Interrupts ................................................................................................ 558 5.7.3 Manual Interrupt Processing (polling) ........................................................................ 560 5.7.4 Traps .............................................................................................................. 561 5.8 Differences Between C64x and C64x+ CPU Interrupts ............................................................. 562 6 C64x+ CPU Exceptions ..................................................................................................... 563 6.1 Overview .................................................................................................................. 564 6.1.1 Types of Exceptions and Signals Used ...................................................................... 564 6.1.2 Exception Service Vector ...................................................................................... 565 6.1.3 Summary of Exception Control Registers ................................................................... 565 6.2 Exception Control ........................................................................................................ 567 6.2.1 Enabling and Disabling External Exceptions ................................................................ 567 6.2.2 Pending Exceptions ............................................................................................. 567 6.2.3 Exception Event Context Saving .............................................................................. 567 6.2.4 Returning From Exception Servicing ......................................................................... 568 6.3 Exception Detection and Processing .................................................................................. 569 6.3.1 Setting the Exception Pending Flag .......................................................................... 569 6.3.2 Conditions for Processing an External Exception .......................................................... 569 6.3.3 Actions Taken During External Exception (EXCEP) Processing ......................................... 572 5 SPRU732J–July 2010 Contents Copyright © 2010, Texas Instruments Incorporated www.ti.com 6.3.4 Nested Exceptions .............................................................................................. 572 6.4 Performance Considerations ........................................................................................... 572 6.4.1 General Performance ........................................................................................... 572 6.4.2 Pipeline Interaction ............................................................................................. 572 6.5 Programming Considerations .......................................................................................... 575 6.5.1 Internal Exceptions ............................................................................................. 575 6.5.2 Internal Exception Report Register (IERR) .................................................................. 575 6.5.3 Software Exception ............................................................................................. 576 7 Software Pipelined Loop (SPLOOP) Buffer .......................................................................... 577 7.1 Software Pipelining ...................................................................................................... 578 7.2 Software Pipelining ...................................................................................................... 578 7.3 Terminology ............................................................................................................... 579 7.4 SPLOOP Hardware Support ............................................................................................ 579 7.4.1 Loop Buffer ...................................................................................................... 579 7.4.2 Loop Buffer Count Register (LBC) ............................................................................ 579 7.4.3 Inner Loop Count Register (ILC) .............................................................................. 579 7.4.4 Reload Inner Loop Count Register (RILC) ................................................................... 580 7.4.5 Task State Register (TSR), Interrupt Task State Register (ITSR), and NMI/Exception Task State Register (NTSR) ................................................................ 580 7.5 SPLOOP-Related Instructions .......................................................................................... 580 7.5.1 SPLOOP, SPLOOPD, and SPLOOPW Instructions ........................................................ 580 7.5.2 SPKERNEL and SPKERNELR Instructions ................................................................. 581 7.5.3 SPMASK and SPMASKR Instructions ....................................................................... 582 7.6 Basic SPLOOP Example ................................................................................................ 583 7.6.1 Some Points About the Basic SPLOOP Example .......................................................... 584 7.6.2 Same Example Using the SPLOOPW Instruction .......................................................... 585 7.6.3 Some Points About the SPLOOPW Example ............................................................... 586 7.7 Loop Buffer ............................................................................................................... 586 7.7.1 Software Pipeline Execution From the Loop Buffer ........................................................ 587 7.7.2 Stage Boundary Terminology ................................................................................. 587 7.7.3 Loop Buffer Operation .......................................................................................... 588 7.8 Execution Patterns ....................................................................................................... 590 7.8.1 Prolog, Kernel, and Epilog Execution Patterns ............................................................. 590 7.8.2 Early-Exit Execution Pattern ................................................................................... 591 7.8.3 Reload Execution Pattern ...................................................................................... 592 7.9 Loop Buffer Control Using the Unconditional SPLOOP(D) Instruction ............................................ 594 7.9.1 Initial Termination Condition Test and ILC Decrement ..................................................... 594 7.9.2 Stage Boundary Termination Condition Test and ILC Decrement ....................................... 594 7.9.3 Using SPLOOPD for Loops with Known Minimum Iteration Counts ..................................... 595 7.9.4 Program Memory Fetch Enable Delay During Epilog ...................................................... 596 7.9.5 Stage Boundary and SPKERNEL(R) Position .............................................................. 596 7.9.6 Loop Buffer Reload ............................................................................................. 596 7.9.7 Restrictions on Accessing ILC and RILC .................................................................... 600 7.10 Loop Buffer Control Using the SPLOOPW Instruction .............................................................. 600 7.10.1 Initial Termination Condition Using the SPLOOPW Condition ........................................... 601 7.10.2 Stage Boundary Termination Condition Using the SPLOOPW Condition .............................. 601 7.10.3 Interrupting the Loop Buffer When Using SPLOOPW .................................................... 601 7.10.4 Under-Execution of Early Stages of SPLOOPW When Termination Condition Becomes True While Interrupt Draining ........................................................................................ 602 7.11 Using the SPMASK Instruction ......................................................................................... 602 7.11.1 Using uploads/Voyage/ reference-guide 2 .pdf